Hung Q. Le IBM Systems and Technology Group, 11400 Burnet Road, Austin, Texas 78758 (hungus.ibm.com). Mr. Le is a Distinguished Engineer in the POWER* microarchitecture development team of the Systems and Technology Group. He joined IBM in 1979 after graduating from Clarkson University with a B.S. degree in electrical and computer engineering. He has worked on the development of several IBM mainframe and POWER and PowerPC processors. His technical interests are in the field of processor design involving multithreading, superscalar, and out-of-order design.

William J. Starke IBM Systems and Technology Group, 11400 Burnet Road, Austin, Texas 78758 (wstarkeus.ibm.com). Mr. Starke is a Senior Technical Staff Member in the POWER development team of the Systems and Technology Group. He joined IBM in 1990 after graduating from Michigan Technological University with a B.S. degree in computer science. After several years of cache hierarchy and symmetric multiprocessor (SMP) hardware performance analysis for both IBM mainframe and POWER server development programs, he transitioned to logic design and microarchitecture development, working initially on the POWER4 and POWER5 programs. Mr. Starke led the development of the POWER6 cache hierarchy and SMP interconnect, and now serves as the Chief Architect for the POWER7* storage hierarchy.

J. Stephen Fields IBM Systems and Technology Group, 11400 Burnet Road, Austin, Texas 78758 (sfieldsus.ibm.com). Mr. Fields is a Distinguished Engineer in the POWER development team of the Systems and Technology Group. He joined IBM in 1988 after graduating from the University of Illinois with a B.S. degree in electrical engineering. He has worked on a variety of development efforts ranging from the IBM Micro Channel*, Peripheral Component Interface, and memory controllers, and he has been working on microprocessor cache hierarchy and SMP development since the POWER4 program. Mr. Fields currently is responsible for post-silicon validation for POWER6 and POWER7 processors.

Francis P. O'Connell IBM Systems and Technology Group, 11400 Burnet Road, Austin, Texas 78758 (oconnellus.ibm.com). Mr. O'Connell is a Senior Technical Staff Member in the POWER system development area. For the past 22 years, he has focused on scientific and technical computing performance within IBM, including microprocessor and systems design, compiler performance, algorithm development, and application tuning. Mr. O'Connell joined IBM in 1981 after receiving a B.S. degree in mechanical engineering from the University of Connecticut. He subsequently earned an M.S. degree in engineering-economic systems from Stanford University.

Dung Q. Nguyen IBM Systems and Technology Group, 11400 Burnet Road, Austin, Texas 78758. Mr. Nguyen is a Senior Engineer in the POWER development team of the Systems and Technology Group. He joined IBM in 1986 after graduating from the University of Michigan with an M.S. degree in materials engineering. He has worked on the development of several processors including POWER3*, POWER4, POWER5, and POWER6. He is currently working on the POWER7 microprocessor. Mr. Nguyen's technical interests are in the field of processor design involving instruction sequencing and multithreading.

Bruce J. Ronchetti IBM Systems and Technology Group, 11400 Burnet Road, Austin, Texas 78758 (ronchettus.ibm.com). Mr. Ronchetti is a Senior Technical Staff Member in the POWER system development area. For the past ten years, he has focused on processor core microarchitecture development, particularly in load and store units. Mr. Ronchetti joined IBM in 1979 after receiving a B.S. degree in electrical engineering from Lafayette College.

Wolfram M. Sauer IBM Systems and Technology Group, 11400 Burnet Road, Austin, Texas 78758 (wsauerus.ibm.com). Mr. Sauer is a Senior Technical Staff Member in the processor development area. He received a diploma degree (Diplom-Informatiker) in computer science from the University of Dortmund, Germany, in 1984. He subsequently joined IBM at the development laboratory in Boeblingen, Germany, and worked on the S/370* (later S/390* and zSeries*) processor design, microcode, and tools. He joined IBM Austin in 2002 to work on the POWER6 project.

Eric M. Schwarz IBM Systems and Technology Group, 2455 South Road, Poughkeepsie, New York 12601 (eschwarzus.ibm.com). Dr. Schwarz is a Distinguished Engineer in zSeries, iSeries*, and pSeries* processor development. He received a B.S. degree in engineering science from The Pennsylvania State University, an M.S. degree in electrical engineering from Ohio University, and a Ph.D. degree in electrical engineering from Stanford University. He joined IBM at the Endicott Glendale Laboratories working on follow-ons to the Enterprise System/4381* and Enterprise System/9370* computers. He later worked on the G4, G5, G6, z900, z990, z9* 109, and POWER6 processor-based computers. He led the development of floating-point units for all these computers and was also Chief Engineer of the z900. Dr. Schwarz is active in the IEEE Symposium on Computer Arithmetic and has been on the program committee since 1993.

Michael T. (Mike) Vaden IBM Systems and Technology Group, 11400 Burnet Road, Austin, Texas 78758 (mtvadenus.ibm.com). Mr. Vaden is a Senior Engineer. He has worked on many of the POWER and PowerPC processors including the logic design for the fixed-point unit in the RIOS Single Chip, PowerPC 601 microprocessor, POWER5 and POWER6 processors, and the L2 cache control logic for the POWER3 and POWER3+ processors. Mr. Vaden holds a B.S.E.E degree from Texas A&M University and an M.S.E.E degree from the University of Texas at Austin.

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