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IBM Journal of Research and Development
IBM POWER6 Microprocessor Technology   Volume 51, Number 6, 2007
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System power management support in the IBM POWER6 microprocessor - References

 by M. S. Floyd,
S. Ghiasi,
T. W. Keller,
K. Rajamani,
F. L. Rawson,
J. C. Rubio,
and M. S. Ware
References

  1. K. Bernstein, D. J. Frank, A. E. Gattiker, W. Haensch, B. L. Ji, S. R. Nassif, E. J. Nowak, D. J. Pearson, and N. J. Rohrer, “High-Performance CMOS Variability in the 65-nm Regime and Beyond,” IBM J. Res. & Dev. 50, No. 4/5, 433–449 (2006).
  2. D. M. Dreps, F. D. Ferraiolo, and K. C. Gower, “Elastic Interface Apparatus and Method Therefor,” U.S. Patent No. 6,334,163, December 25, 2001.
  3. F. Ferraiolo, E. Cordero, D. Dreps, M. Floyd, K. Gower, and B. McCredie, “POWER4 Synchronous Wave-Pipelined Interface,” Hot Chips 11: A Symposium on High-Performance Chips, August 15–17, 1999; see http://www.hotchips.org/archives/hc11/2_Mon/hc99.s2.2.Ferriaolo.pdf.
  4. C. Lefurgy, K. Rajamani, F. Rawson, W. Felter, M. Kistler, and T. W. Keller, “Energy Management for Commercial Servers,” IEEE Computer, December 2003, pp. 30–48.
  5. W. Felter, K. Rajamani, T. Keller, and C. Rusu, “A Performance-Conserving Approach for Reducing Peak Power Consumption in Server Systems,” Proceedings of the 19th ACM International Conference on Supercomputing, Cambridge, MA, June 20–22, 2005, pp. 293–302.
  6. A. Drake, R. Senger, H. Deogun, G. Carpenter, S. Ghiasi, T. Nguyen, N. James, M. Floyd, and V. Pokala, “A Distributed Critical-Path Timing Monitor for a 65nm High-Performance Microprocessor,” Proceedings of the International Solid-State Circuits Conference, February 11–15, 2007, pp. 398–399.
  7. K. Rajamani, H. Hanson, J. Rubio, S. Ghiasi, and F. Rawson, “Application-aware Power Management,” Proceedings of the 2006 IEEE International Symposium on Workload Characterization, San Jose, CA, October 2006, pp. 39–48.
  8. R. Kotla, S. Ghiasi, T. Keller, and F. Rawson, “Scheduling Processor Voltage and Frequency in Server and Cluster Systems,” Proceedings of the 19th International Parallel and Distributed Processing Symposium, April 4–8, 2005.
  9. K. Rajamani, H. Hanson, J. C. Rubio, S. Ghiasi, and F. L. Rawson, “Online Power and Performance Estimation for Dynamic Power Management,” Research Report RC-24007, IBM Thomas J. Watson Research Center, Yorktown Heights, NY 10598, July 2006; see http://domino.research.ibm.com/library/cyberdig.nsf/398c93678b87a12d8525656200797aca/
    8a07e78644cb39d9852571b200687e3b?OpenDocument    .
  10. C. Isci, G. Contreras, and M. Martonosi, “Hardware Performance Counters for Detailed Runtime Power and Thermal Estimations: Experiences and Proposals,” Hardware Performance Monitor Design and Functionality Workshop, February 2005.
  11. M. S. Floyd, L. S. Leitner, and K. F. Reick, “Method and Apparatus for a High-Speed Serial Communications Bus Protocol with Positive Acknowledgement,” U.S. Patent No. 6,529,979, March 4, 2003.
  12. Phillips Semiconductors, “The I2C-Bus Specification,” Version 2.1, white paper; see http://www.nxp.com/acrobat_download/literature/9398/39340011.pdf.
  13. H.-Y. McCreary, M. A. Broyles, M. S. Floyd, A. J. Geissler, S. P. Hartman, F. L. Rawson, T. J. Rosedahl, J. C. Rubio, and M. S. Ware, “EnergyScale for IBM POWER6 Microprocessor-Based Systems,” IBM J. Res. & Dev. 51, No. 6, 775–786 (2007, this issue).
  14. P. K. Popa, “Managing Server Energy Consumption Using IBM PowerExecutive,” white paper (May 2006); see ftp://ftp.software.ibm.com/common/ssi/rep_wh/n/XSW02410USEN/XSW02410USEN.PDF.


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