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IBM Journal of Research and Development
IBM POWER6 Microprocessor Technology   Volume 51, Number 6, 2007
Table of contents: HTMLPDF This article: HTMLPDF   Copyright info

IBM POWER6 accelerators: VMX and DFU - References

 by L. Eisen,
J. W. Ward III,
H.-W. Tast,
N. Mäding,
J. Leenstra,
S. M. Mueller,
C. Jacobi,
J. Preiss,
E. M. Schwarz,
and S. R. Carlough
References

  1. Freescale Semiconductor, AltiVec™ Technology Programming Environments Manual, 2006; see http://www.freescale.com/files/32bit/doc/ref_manual/ALTIVECPEM.pdf.
  2. M. S. Schmookler, M. Putrino, C. Roth, M. Sharma, A. Mather, J. Tyler, H. Van Nguyen, M. N. Pham, and J. Lent, “A Low-Power, High-Speed Implementation of a PowerPC™ Microprocessor Vector Extension,” Proceedings of the 14th IEEE Symposium on Computer Arithmetic, Adelaide, Australia, 1999, pp. 14–16.
  3. M. M. Ziegler and M. R. Stan, “A Unified Design Space for Regular Parallel Prefix Adders,” Proceedings of the Conference on Design, Automation and Test in Europe, Paris, France, 2004, pp. 1386–1387.
  4. N. Mäding, J. Leenstra, J. Pille, R. Sautter, S. Buttner, S. Ehrenreich, and W. Haller, “The Vector Fixed Point Unit of the Synergistic Processor Element of the Cell Architecture Processor,” Proceedings of the 31st European Solid-State Conference, Grenoble, France, 2005, pp. 203–206.
  5. S. D. Trong, M. Schmookler, E. M. Schwarz, and M. Kroener, “POWER6 Binary Floating-Point Unit,” Proceedings of the 18th IEEE Symposium on Computer Arithmetic (ARITH18), Montpellier, France, 2007, pp. 77–86.
  6. ANSI/IEEE Standard 754-1985, “IEEE Standard for Binary Floating-Point Arithmetic,” ©1985 IEEE; see http://754r.ucbtest.org/standards/754xml.html.
  7. S. M. Mueller and W. J. Paul, Computer Architecture: Complexity and Correctness, Springer-Verlag, Berlin, Germany, 2000, pp. 351–436.
  8. J. Gosling, B. Joy, and G. Steele, The Java™ Language Specification, Addison-Wesley, Boston, MA, 1996.
  9. E. M. Schwarz, “Binary Floating-Point Unit Design: The Fused Multiply–Add Dataflow,” High-Performance Energy-Efficient Microprocessor Design, V. G. Oklobdzija and R. K. Krishnamurthy, Eds., Springer, Dordrecht, The Netherlands, 2006, pp. 189–208.
  10. X. Y. Yu, Y.-H. Chan, M. Kelly, E. Schwarz, B. Curran, and B. Fleischer, “A 5GHz+ 128-bit Binary Floating-Point Adder for the POWER6 Processor,” Proceedings of the European Solid-State Circuits Conference, Montreux, Switzerland, 2006, pp. 166–169.
  11. H.-J. Oh, S. M. Mueller, C. Jacobi, K. D. Tran, S. R. Cottier, B. W. Michael, H. Nishikawa, et al., “A Fully Pipelined Single-Precision Floating-Point Unit in the Synergistic Processor Element of a Cell Processor,” IEEE J. Solid-State Circuits 41, No. 4, 759–771 (2006).
  12. ANSI/IEEE, “DRAFT Standard for Floating-Point Arithmetic P754,” Draft 1.2.5, see “Working Group Records,” at http://754r.ucbtest.org/.
  13. M. F. Cowlishaw, “Decimal Floating-Point: Algorism for Computers,” Proceedings of the 16th IEEE Symposium on Computer Arithmetic, 2003, pp. 104–111.
  14. M. Cowlishaw, “Densely Packed Decimal Encoding,” IEE Proceedings—Computers and Digital Techniques 149, No. 3, 102–104 (May 2002).
  15. ANSI/IEEE Standard 854-1987, “IEEE Standard for Radix-Independent Floating-Point Arithmetic,” ©1987 IEEE; see http://754r.ucbtest.org/standards/854xml.html.
  16. E. M. Schwarz and S. Carlough, “POWER6 Decimal Divide,” submitted to the 18th IEEE International Conference on Application-Specific Systems, Architectures and Processors, Montreal, Canada, July 2007.
  17. R. K. Richards, Arithmetic Operations in Digital Computers, D. Van Nostrand Company, Inc., New York, 1955, pp. 247–285.


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