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IBM Journal of Research and Development
IBM POWER6 Microprocessor Technology   Volume 51, Number 6, 2007
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Power-constrained high-frequency circuits for the IBM POWER6 microprocessor - References

 by B. Curran,
E. Fluhr,
J. Paredes,
L. Sigal,
J. Friedrich,
Y.-H. Chan,
and C. Hwang
References

  1. B. Curran, B. McCredie, L. Sigal, E. Schwarz, B. Fleischer, Y. H. Chan, D. Webber, M. Vaden, and A. Goyal, “4GHz+ Low-Latency Fixed-Point and Binary Floating-Point Execution Units for the POWER6 Processor,” Solid-State Circuits, 2006 IEEE ISSCC Digest of Technical Papers, February 6–9, 2006, pp. 436–437.
  2. B. W. Curran, Y. H. Chan, P. T. Wu, P. J. Camporese, G. A. Northrop, R. F. Hatch, L. B. Lacey, J. P. Eckhardt, D. T. Hui, and H. H. Smith, “IBM eServer z900 High-Frequency Microprocessor Technology, Circuits, and Design Methodology,” IBM J. Res. & Dev. 46, No. 4/5, pp. 631–644 (2002).
  3. E. Leobandung, H. Nayakama, D. Mocuta, K. Miyamoto, M. Angyal, H. V. Meer, K. McStay, et al., “High Performance 65 nm SOI Technology with Dual Stress Liner and Low Capacitance SRAM Cell,” Symposium on VLSI Technology, 2005. Digest of Technical Papers, June 14–16, 2005, pp. 126–127.
  4. D. W. Plass and Y. H. Chan, “IBM POWER6 SRAM Arrays,” IBM J. Res. & Dev. 51, No. 6, 747–756 (2007, this issue).
  5. R. Berridge, R. M. Averill III, A. E. Barish, M. A. Bowen, P. J. Camporese, J. DiLullo, P. E. Dudley, et al., “IBM POWER6 Microprocessor Physical Design and Design Methodology,” IBM J. Res. & Dev. 51, No. 6, 685–714 (2007, this issue).
  6. R. J. Restle, T. G. McNamara, D. A. Webber, P. J. Camporese, K. F. Eng, K. A. Jenkins, D. H. Allen, et al., “A Clock Distribution Network for Microprocessors,” J. Solid-State Circuits 36, 792–799 (2001).
  7. M. G. R. Thomson, P. J. Restle, and N. K. James, “A 5GHz Duty-Cycle Correcting Clock Distribution Network for the POWER6 Microprocessor,” Solid-State Circuits, 2006 IEEE ISSCC Digest of Technical Papers, February 6–9, 2006, pp. 1522–1529.
  8. P. J. Restle, R. L Franch, J. K. Norman, W. V. Huott, T. M. Skergan, S. C. Wilson, N. S. Schwartz, and J. G. Clabes, “Timing Uncertainty Measurements on the POWER5 Microprocessor,” IEEE ISSCC Digest of Technical Papers, February 2004, pp. 354–355.
  9. X. Yu, Y. H. Chan, B. Curran, E. Schwarz, B. Fleischer, and M. Kelly, “A 5 GHz+ Binary Floating-Point Adder for the POWER6 Processor,” ESSCIRC 2006, pp. 166–169.
  10. J. D. Warnock, J. M. Keaty, J. Petrovick, J. G. Clabes, C. J. Kircher, B. L. Krauter, P. J. Restle, B. A. Zoric, and C. J. Anderson, “The Circuit and Physical Design of the POWER4 Microprocessor,” IBM J. Res. & Dev. 46, No. 1, pp. 27–52 (2002).
  11. J. Friedrich, B. McCredie, N. James, B. Huott, B. Curran, E. Fluhr, G. Mittal, et al., “Design of POWER6™ Microprocessor,” Proceedings of the International Solid-State Circuits Conference (ISSCC), San Francisco, CA, February 11–15, 2007, Solid-State Circuits, 2007 IEEE ISSCC Digest of Technical Papers.


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