IBM®
Skip to main content
    Country/region [change]    Terms of use
 
 
 
    Home    Products    Services & solutions    Support & downloads    My account    

IBM Journal of Research and Development
IBM POWER6 Microprocessor Technology   Volume 51, Number 6, 2007
Table of contents: HTMLPDF This article: HTMLPDF   Copyright info

IBM POWER6 microprocessor physical design and design methodology - References

 by R. Berridge,
R. M. Averill III,
A. E. Barish,
M. A. Bowen,
P. J. Camporese,
J. DiLullo,
P. E. Dudley,
J. Keinert,
D. W. Lewis,
R. D. Morel,
T. Rosser,
N. S. Schwartz,
P. Shephard,
H. H. Smith,
D. Thomas,
P. J. Restle,
J. R. Ripley,
S. L. Runyon,
and P. M. Williams
References

  1. E. Leobandung, E. Nayakama, H. Mocuta, D. Miyamoto, K. Angyal, M. Meer, H. V. McStay, et al., “High Performance 65 nm SOI Technology with Dual Stress Liner and Low Capacitance SRAM Cell,” 2005 Symposium on VLSI Technology, Digest of Technical Papers, June 14–16, 2005, pp. 126–127.
  2. J. D. Warnock, J. M. Keaty, J. Petrovick, J. G. Clabes, C. J. Kircher, B. L. Krauter, P. J. Restle, B. A. Zoric, and C. J. Anderson, “The Circuit and Physical Design of the POWER4 Microprocessor,” IBM J. Res. & Dev. 46, No. 1, pp. 27–51 (2002).
  3. B. W. Curran, Y. H. Chan, P. T. Wu, P. J. Camporese, G. A. Northrop, R. F. Hatch, L. B. Lacey, J. P. Eckhardt, D. T. Hui, and H. H. Smith, “IBM eServer z900 High-Frequency Microprocessor Technology, Circuits, and Design Methodology,” IBM J. Res. & Dev. 46, No. 4/5, pp. 631–644 (2002).
  4. V. Rao, J. Soreff, T. Brodnax, and R. Mains, “EinsTLT: Transistor Level Timing with EinsTimer,” Proceedings of the International Workshop on Timing Issues (TAU) in the Specification and Synthesis of Digital Systems, March 8–9, 1999, pp. 1–6.
  5. A. R. Conn, K. Scheinberg, and Ph. L. Toint, “A Derivative Free Optimization Algorithm in Practice,” Proceedings of the 7th AIAA/USAF/NASA/ISSMO Symposium on Multidisciplinary Analysis and Optimization, St. Louis, MO, 1998.
  6. P. J. Camporese, A. Deutsch, T. G. McNamara, P. Restle, and D. Webber, “X-Y Grid Tree Tuning Method,” U.S. Patent No. 6,205,571, March 20, 2001.
  7. P. J. Restle, R. L. Franch, N. K. Norman, W. V. Huott, T. M. Skergan, S. C. Wilson, N. S. Schwartz, and J. G. Clabes, “Timing Uncertainty Measurements on the POWER5 Microprocessor,” 2004 IEEE International Solid-States Circuits Conference, Digest of Technical Papers, February 15–19, 2004, pp. 354–355.
  8. M. S. Floyd, S. Ghiasi, T. W. Keller, K. Rajamani, F. L. Rawson, J. C. Rubio, and M. S. Ware, “System Power Management Support in the IBM POWER6 Microprocessor,” IBM J. Res. & Dev. 51, No. 6, pp. 733–746 (2007, this issue).
  9. S. R. Nassif and J. N. Kozhaya, “Fast Power Grid Simulation,” Proceedings of the 37th Design Automation Conference, 2000, pp. 156–161.
  10. J. S. Neely, H. H. Chen, S. G. Walker, J. Venuto, and T. J. Bucelot, “CPAM: A Common Power Analysis Methodology for High-Performance VLSI Design,” IEEE Conference on Electrical Performance of Electronic Packaging, Scottsdale, AZ, October 23–25, 2000, pp. 303–306.
  11. R. M. Averill III, K. G. Barkley, M. A. Bowen, P. J. Camporese, A. H. Dansky, R. F. Hatch, D. E. Hoffman, et al., “Chip Integration Methodology for the IBM S/390 G5 and G6 Custom Microprocessors,” IBM J. Res. & Dev. 43, No. 5/6, pp. 681–706 (1999).
  12. H. Smith, A. Deutsch, S. Mehrotra, D. Widiger, M. Bowen, A. Dansky, G. Kopcsay, and B. Krauter, “R(f)L(f)C Coupled Noise Evaluation of an S/390 Microprocessor Chip,” IEEE Conference on Custom Integrated Circuits, San Diego, May 2001, pp. 237–240.
  13. A. Deutsch, H. H. Smith, B. J. Rubin, B. L. Krauter, and G. V. Kopcsay, “New Methodology for Combined Simulation of Delta-I Noise Interaction with Interconnect Noise for Wide, On-Chip Data-Buses Using Lossy Transmission-Line Power Blocks,” IEEE Transactions on Advanced Packaging, Vol. 29, February 2006, pp. 11–20.
  14. K. L. Shepard and V. Narayanan, “Noise in Deep Submicron Digital Design,” 1996 International Conference on Computer-Aided Design (ICCAD 1996), Digest of Technical Papers, 1996, pp. 524–531.
  15. J. R. Black, “Electromigration—A Brief Survey and Some Recent Results,” IEEE Transactions on Electron Devices, Vol. 16, 1969, pp. 338–347.
  16. J. Friedrich, B. McCredie, N. James, B. Huott, B. Curran, E. Fluhr, G. Mittal, et al., “Design of the POWER6 Microprocessor,” Proceedings of the International Solid-State Circuits Conference (ISSCC), Digest of Technical Papers, San Francisco, CA, February 11–15, 2007, pp. 96–97.


    About IBM    Privacy    Contact