Rex Berridge IBM Systems and Technology Group, 11500 Burnet Road, Austin, Texas 77850 (rexbus.ibm.com). Mr. Berridge is a Senior Engineering Manager in the integration and methodology department. He received a B.S. degree in electrical engineering from Texas A&M University in 1999. He subsequently joined IBM, where he has worked on transistor-level timing. In 2005 he received an IBM Outstanding Innovation Award for his work on POWER5 transistor-level timing.

Robert M. Averill III IBM Systems and Technology Group, 2455 South Road, Poughkeepsie, New York 12601 (averillrus.ibm.com). Mr. Averill is a Senior Technical Staff Member in the iSeries, pSeries, and zSeries* hardware development laboratory in Poughkeepsie, New York. In 1983 he joined IBM at the East Fishkill facility, where he developed advanced VLSI test equipment. He joined the advanced complementary metal-oxide semiconductor (CMOS) microprocessor group in Poughkeepsie in 1994 as a Circuit Designer and is currently the Chip Integration Leader for all iSeries, pSeries, and zSeries microprocessors. Mr. Averill received a B.S.E.E. degree from Northwestern University in 1983 and an M.S.E.E. degree from Syracuse University in 1990. He has received three IBM Outstanding Technical Achievement Awards, one IBM Outstanding Innovation Award, and one IBM Technical Corporate Award for his work in chip integration.

Arnold E. Barish IBM Systems and Technology Group, 2455 South Road, Poughkeepsie, New York 12601 (barishus.ibm.com). Mr. Barish is a Senior Technical Staff Member working in the areas of advanced technology development, ground rules, physical verification, and library support. He received a B.S.E.E. degree from the City College of New York in 1968 and an M.S.E.E. and M.S.C.I.S. from Syracuse University in 1971 and 1977, respectively. He joined IBM in 1968 working on circuit design and I/O wiring rules and later on technology development, ground rules, physical verification, and library applications. Mr. Barish holds several patents and has received a division award for his work on H2 library development, as well as three Outstanding Technical Achievement Awards for his work on H5, POWER4, and POWER5 processor library development.

Michael A. Bowen IBM Systems and Technology Group, 2455 South Road, Poughkeepsie, New York 12601 (MichaelBowenus.ibm.com). Mr. Bowen is a Senior Programmer in the iSeries, pSeries, and zSeries hardware development laboratory in Poughkeepsie, New York. In 1989, he joined IBM at the Kingston facility, where he worked with a team developing timing-driven placement and wiring methodologies. He joined the microprocessor team in Austin, Texas, in 1994 and continued to develop integration tools and methodologies to support the IBM RS/6000* and chips developed in collaboration with Motorola. He joined the advanced CMOS microprocessor group in Poughkeepsie in 1997 as a tool developer and is currently the Tools/Methodology Leader for zSeries systems. Mr. Bowen received a B.A. in math and computer science from the State University of New York at Potsdam in 1988 and an M.S. in computer science from Rensselaer Polytechnic Institute in 1992. He has received two Outstanding Technical Achievement and two Outstanding Contribution Awards for his work in chip integration. He also has four patents in various physical design processes.

Peter J. Camporese IBM Systems and Technology Group, 2455 South Road, Poughkeepsie, New York 12601 (pcampus.ibm.com). Mr. Camporese is a Senior Technical Staff Member at the IBM development laboratory, working on microprocessor physical architecture and integration. Mr. Camporese received a B.S. degree in electrical engineering from the Polytechnic University in 1988 and an M.S. degree in computer engineering from Syracuse University. He joined the IBM data systems division in Poughkeepsie, New York, in 1988, where he has worked on system performance, circuit design, physical design, and chip integration. He was the Technical Team Leader and Chief Physical Design Architect for the G4 and G7 CMOS zSeries microprocessors. He holds 12 U.S. patents and is a coauthor of several papers on high-speed microprocessor design. He has received an IBM Corporate Award for IBM eServer z900 microprocessor development and several IBM Outstanding Technical Achievement and Outstanding Innovation Awards for microprocessor physical design, integration, and tools development. He currently manages the physical design and integration development efforts for future IBM eServer microprocessors.

Jack DiLullo IBM Systems and Technology Group, 11400 Burnett Road, Austin, Texas 78758 (dilullous.ibm.com). Mr. DiLullo is a Senior Engineer working on the integration and timing team in Austin, Texas. He received a B.S. degree in electrical engineering at Polytechnic Institute of New York in 1983 and joined IBM Austin. There, Mr. DiLullo worked in the design verification group involved in timing verification and signoff for mainframe designs. He received an M.S. degree in computer engineering from Syracuse University in 1988 and later joined IBM Boca Raton in 1994 working on IBM OS/2* operating system performance. After moving to Austin in 1996, Mr. DiLullo joined IBM EDA as an application engineer in support of IBM CMOS microprocessor designs before becoming a member of the POWER4 team working on timing methodology development and timing closure. Currently, Mr. DiLullo specializes in global timing methodology for the pSeries, zSeries, and gaming chips, as well as pSeries global chip timing closure.

Peter E. Dudley IBM Systems and Technology Group, 2455 South Road, Poughkeepsie, New York 12601 (pdudleyus.ibm.com). Mr. Dudley is an Advisory Engineer in the integration and methodology department. He received a B.S. degree in computer science and an M.S. degree in electrical engineering in 1991 and 1995, respectively, from the University of Vermont in Burlington. In 1994, he joined IBM at its Burlington, Vermont, facility and worked in the PowerPC* processor hardware development laboratory developing tools and methodologies concentrating on the data management and auditing of advanced microprocessor designs. In 1996, he joined the POWER4 processor hardware development laboratory in Fishkill and then relocated to the IBM site in Poughkeepsie. He received Outstanding Technical Achievement Awards for his audit methodology work and for his work on the POWER5 processor tools and methodology. He is the primary owner of a patent on circuit delay abstraction and is author or coauthor of three technical papers. He is currently Infrastructure Tools Leader of all IBM server and games microprocessor development projects.

Joachim Keinert IBM Systems and Technology Group, Boeblingen Development Laboratory, Schoenaicherstrasse 220, 71032 Boeblingen, Germany (keinertde.ibm.com). Mr. Keinert received an M.S. degree in electrical engineering from the Technical University of Stuttgart, Germany, in 1980. He joined IBM in 1979 to work on bipolar circuit design. In 1982, he started to work on CMOS circuit tool development and chip design methodologies. Since then, he has been involved in the development of design tools for all IBM CMOS mainframe processors. His work also covers innovative technologies such as FinFETs and he holds several patents in various areas. Currently, Mr. Keinert is a focal point for circuit design tools for future IBM eServer processors.

David W. Lewis IBM Systems and Technology Group, 2455 South Road, Poughkeepsie, New York 12601 (dlewisus.ibm.com). Mr. Lewis is a Senior Engineer in the iSeries, pSeries, and zSeries hardware development laboratory in Poughkeepsie, New York. Mr. Lewis received a B.S. degree in computer systems engineering and an M.S. degree in computer science from Rensselaer Polytechnic Institute in 1995, and 2001, respectively. In 1995, he joined IBM at its Burlington, Vermont, facility and worked in the PowerPC processor hardware development laboratory developing circuit design tools for advanced microprocessor design. In 1996, he joined the POWER4 processor hardware development laboratory in Fishkill, New York, where he continued his work in the area of circuit design tool development. Currently, Mr. Lewis is the zSeries tools leader, along with being the physical design automation leader for all iSeries, pSeries, and zSeries microprocessors.

Robert D. Morel IBM Systems and Technology Group, 11400 Burnett Road, Austin, Texas 78758 (rmorelus.ibm.com). Mr. Morel is a Senior Engineer in the iSeries, pSeries, and zSeries hardware development laboratory in Austin, Texas. In 1993 he joined IBM at its Burlington, Vermont, facility and worked in the PowerPC hardware development laboratory developing tools and methodologies for advanced microprocessor design. In 1996 he joined the POWER4 hardware development laboratory in Fishkill, New York, where he continued his work in the area of tools and methodology development. Mr. Morel received B.S.E.E. and M.S.E.E. degrees in 1992 and 1996, respectively, from the University of Vermont in Burlington. He has received an Outstanding Technical Achievement Award for his work in tools and methodology development.

Thomas Rosser IBM Systems and Technology Group, 11400 Burnett Road, Austin, Texas 78758 (rosserus.ibm.com). Mr. Rosser is a Senior Technical Staff Member. He received his B.S. degree in electrical engineering at the University of Missouri at Columbia in 1976, and he joined IBM in Fishkill, New York. In his 30 years in design automation tools at IBM, he has worked in test generation, fault simulation, software simulation, hardware simulation, integrated tools development, design methodologies, circuit characterization and rules, static timing, designer productivity tools and interfaces, language parsing, design verification, logic synthesis, and physical design optimization. He holds 12 patents and serves on the Patent Review Board for the Systems and Technology Group in Austin, Texas. He currently leads the RLM flow for all IBM processors.

Nicole S. Schwartz IBM Systems and Technology Group, 11400 Burnet Road, Austin, Texas 78758 (nschwartus.ibm.com). Miss Schwartz is a Staff Engineer in the zSeries/pSeries integration and tools department in Austin, Texas. She joined IBM in 2001 as a member of the chip integration team for the POWER family of processors. She has continued to work in unit and chip integration on the pSeries and zSeries chips with a primary focus on global clock distribution tools and methodology. Miss Schwartz received a B.S.E. in electrical engineering and computer science from Duke University in 2001 and an M.S.E. in computer engineering from the University of Texas at Austin in 2006.

Philip Shephard IBM Systems and Technology Group, 11500 Burnet Road, Austin, Texas 77850 (shephardus.ibm.com). Mr. Shephard is a Senior Engineer in the PCORE/SRAM design department. He received a B.S.E.E. degree from DeVry Institute of Technology in 1977 and an M.S. degree in computer science from Union College in 1984. He joined IBM in 1978. He worked on various aspects of design for testability (DFT) through 2001 when he took an assignment to drive the implementation and bring-up of transistor-level timing analysis on SRAMs. He holds ten patents in the fields of DFT and timing analysis, with two more pending, and he has received two IBM Outstanding Technical Achievement Awards.

Howard H. Smith 2455 South Road, Poughkeepsie, New York 12601 (smithhus.ibm.com). Mr. Smith received a B.S. and an M.S. degree in electrical engineering from the New Jersey Institute of Technology, Newark, New Jersey, in 1984 and 1985, respectively. He joined IBM in 1984 as an integrated circuit engineer at its semiconductor development laboratory in Fishkill, New York, working in the area of high-performance gate array designs. Mr. Smith is currently a Senior Engineer at the IBM Systems and Technology group in Poughkeepsie, New York, where he is responsible for electrical analysis issues associated with high-density CMOS circuit technology and package-related products. His recent assignments include the development of on-chip noise and power grid verification processes for the IBM processor designs. His expertise lies in the area of electrical noise modeling and prediction at system-level computer operation. He has coauthored several papers on system-level noise prediction, on-chip interconnects, and electromagnetic characterization of connectors and antennas. He has several patents in his field of expertise.

Dave Thomas IBM Systems and Technology Group, 3039 Cornwallis Road, Research Triangle Park, North Carolina 27709 (thomasdrus.ibm.com). Mr. Thomas is a Senior Engineer. He received his B.S. degree in electrical engineering at the University of Missouri at Columbia in 1977 and completed graduate coursework at the University of Kentucky. He joined IBM in 1977 and worked as a DRAM Circuit Designer. Over his 29-year career with IBM, he has performed in many roles including management, analog circuit design, modem design, logic design, dc/dc converter design, and tools software development. He received an Outstanding Technical Achievement Award for Smart Power development and holds seven patents in power control systems, unique circuit topologies for integrating dc/dc regulators on VLSI chips, and nonvolatile memory cells. He is currently responsible for development of power/performance/yield estimation tools for zSeries and pSeries processors.

Phillip J. Restle IBM Research Division, Thomas J. Watson Research Center, P.O. Box 218, Yorktown Heights, New York 10598 (restleus.ibm.com). Dr. Restle received a Ph.D. in physics from the University of Illinois in 1986. At IBM Research, he has worked on CMOS modeling, package test, DRAM variable retention time, and high-speed interconnect modeling. For the past decade, he has concentrated on methodology, tools, and designs for high-performance clock distribution networks. He has contributed to more than a dozen high-performance microprocessors including all recent IBM mainframes, the POWER4, POWER5, and POWER6 microprocessors, and the Microsoft Xbox 360** entertainment system and the Sony Cell Broadband Engine** processors.

John R. Ripley IBM Systems and Technology Group, 11500 Burnet Road, Austin, Texas 77850 (ripus.ibm.com). Mr. Ripley is a Senior Technical Staff Member in the iSeries, pSeries, and zSeries hardware development laboratory in Austin, Texas. He received a B.S. degree in electrical engineering from the University of Tennessee and an M.S.E.E. degree from the University of Texas in 1985. He joined IBM in 1980 and has worked on advanced CMOS microprocessor development spanning the POWER microprocessor to the current POWER6 microprocessor. Over his career with IBM, he has performed many roles including management, logic design, circuit design, DFT, integration tools and methodology development, and chip integration. He is currently the lead chip integrator for the POWER6 chip.

Stephen L. Runyon IBM Systems and Technology Group, 11500 Burnet Road, Austin, Texas 78758 (steveus.ibm.com). Mr. Runyon is a Senior Technical Staff Member working in the areas of process technology, physical design and circuit layout, yield, design for manufacturability and physical verification. He received a B.E.E. degree from the Georgia Institute of Technology in 1980 and joined IBM in 1981, where he has worked in circuit design, layout, and checking, and later in chip integration and technology. He received an M.S.E.E. degree from the University of Texas in 1985 and holds numerous patents in various areas. He has received two Outstanding Technical Achievement Awards for his work on POWER4 and POWER5 processor designs.

Patrick M. Williams IBM Systems and Technology Group, 2070 Route 52, Hopewell Junction, New York 12533 (patricwus.ibm.com). Mr. Williams is Senior Engineering Manager of the transistor-level automation department in the engineering design automation group. In 1984, he joined IBM at the East Fishkill facility, where he developed VLSI high-speed memory test systems. In 1992, he joined the advanced CMOS microprocessor team in Poughkeepsie, New York. He was initially part of the processor SRAM development team and in 1994 joined the CAD development team in support of the zSeries line of processors. He was the Lead Circuit Methodologist in support of the POWER6 processor development. Mr. Williams has been involved in many aspects of CAD development related to high-speed microprocessors, including timing, noise, power, internal resistance drop and electromigration analysis, device and parasitic extraction, chip integration, circuit optimization, electrical checking, and layout automation. He received a B.S.E.E. degree from Pennsylvania State University in 1984. Mr. Williams holds several U.S. patents and has received four IBM Outstanding Technical Achievement Awards.

*Trademark, service mark, or registered trademark of International Business Machines Corporation in the United States, other countries, or both.
**Trademark, service mark, or registered trademark of Microsoft Corporation or Sony Computer Entertainment, Inc., in the United States, other countries, or both.