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IBM Journal of Research and Development
Cell Broadband Engine Technology and Systems   Volume 51, Number 5, 2007
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Cell Broadband Engine processor: Design and implementation - References

 by M. W. Riley,
J. D. Warnock,
and D. F. Wendel
References

  1. D. C. Pham, T. Aipperspach, D. Boerstler, M. Bolliger, R. T. Chaudhry, D. Cox, P. Harvey, et al., “The Design and Implementation of a First-Generation Cell Processor,” ISSCC Digest of Technical Papers, February 2005, pp. 184–185.
  2. B. Flachs, S. Asano, S. H. Dhong, H. P. Hofstee, G. Gervais, R. Kim, T. Le, et al., “The Microarchitecture of the Streaming Processor for a Cell Processor,” ISSCC Digest of Technical Papers, February 2005, pp. 134–135.
  3. T. Asano, S. H. Dhong, O. Takahashi, M. White, T. Nakazato, J. Silberman, A. Kawasumi, and H. Yoshihara, “A 4.8GHz Fully Pipelined Embedded SRAM in the Streaming Processor of a Cell Processor,” ISSCC Digest of Technical Papers, February 2005, pp. 486–487.
  4. “RISCWatch Debugger User's Manual,” Seventeenth Edition, IBM Corporation, January 2007, http://www.ibm.com/chips/techlib/techlib.nsf/techdocs/8A70ED3C8215AC5E872569D90050295E.
  5. P. J. Restle, C. A. Carter, J. P. Eckhardt, B. L. Krauter, B. D. McCredie, K. A. Jenkins, A. J. Weger, and A. V. Mule, “The Clock Distribution of the Power4 Microprocessor,” IEEE International Solid-State Circuits Conference Digest of Technical Papers, 2002, pp. 144–145.
  6. D. W. Boerstler and K. A. Jenkins, “A Phase-Locked Loop Clock Generator for a 1 GHz Microprocessor,” Symposium on VLSI Circuits (VLSI 1998), Digest of Technical Papers, June 11–13, 1998, pp. 212–213.
  7. D. Boerstler, K. Miki, E. Hailu, H. Kihara, E. Lukes, J. Peter, S. Pettengill, J. Qi, J. Strom, and M. Yoshida, “A 10+ GHz Low Jitter Wide Band PLL in 90 nm PD SOI CMOS Technology,” Symposium on VLSI Circuits, Digest of Technical Papers, June 17–19, 2004, pp. 228–231.
  8. D. W. Boerstler, “Interleaved VCO with Balanced Feedforward,” U.S. Patent No. 6,744,326, June 1, 2004.
  9. S. K. H. Fung, N. Zamdmer, P. J. Oldiges, J. Sleight, A. Mocuta, M. Sherony, S. H. Lo, et al., “Controlling Floating-Body Effects for 0.13 μm and 0.10 μm SOI CMOS,” Technical Digest of International Electron Devices Meeting (IEDM 2000), December 10–13, 2000, pp. 231–234.
  10. K. L. Shepard, V. Narayannan, and R. Rose, “Harmony: Static Noise Analysis of Deep Submicron Digital Integrated Circuits,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 18, No. 8, August 1999, pp. 1132–1150.
  11. S. Lee, S. S. Van Au, and K. P. Moran, “Constriction/Spreading Resistance Model for Electronics Packaging,” Proceedings of the ASME/JSME Thermal Engineering Conference, 4, 1995, pp. 199–206.
  12. K. Yazawa and M. Ishizuka, “Thermal Modeling with Transfer Function for the Transient Chip-On-Substrate Problem,” Thermal Sci. Eng. 13, No. 1, pp. 37–40 (2005).
  13. K. E. Goodson, Y. S. Ju, and M. Asheghi, “Thermal Phenomenon in Semiconductor Devices and Interconnects,” Chapter 7, Miroscale Energy Transport, C. L. Tien, A. Majumdar, and F. M. Gerner, Editors, Taylor & Francis, New York, 1998, pp. 229–294.


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