Yang Liu Lawrence Livermore National Laboratory, 7000 East Avenue, Livermore, California 94550 (liu24llnl.gov). Dr. Liu is a Computer Scientist at Lawrence Livermore National Laboratory (LLNL). In 2004, he received a Ph.D. degree in computer science from the University of California, Davis. Dr. Liu has directed his recent efforts at LLNL to applying hardware acceleration to data and computation-intensive algorithms using commodity computer processors. His research interests include computer graphics, scientific visualization, high-performance computing, and bioinformatics.

Holger Jones Lawrence Livermore National Laboratory, 7000 East Avenue, Livermore, California 94550 (holgerjonesllnl.gov). Mr. Jones is a Projects Team Leader and Senior Developer at LLNL, with experience in signal processing, systems programming, distributed computing, control systems engineering, and scientific visualization. He received an M.S. degree in electrical and computer engineering from the University of California, Davis, in 2002.

Sheila Vaidya Lawrence Livermore National Laboratory, 7000 East Avenue, Livermore, California 94550 (vaidya1llnl.gov). Dr. Vaidya is an embedded computing and data processing solutions program leader at LLNL. Her background is in high-performance computing, information technology, and digital imaging, and she has extensive experience in microelectronics systems and technology, semiconductor devices, integrated-circuit design and fabrication, and chip-manufacturing infrastructure. She received a Ph.D. degree in materials science and solid-state physics from the State University of New York, Stony Brook, in 1979. She has more than 100 scientific publications and holds 14 patents. Dr. Vaidya is currently responsible for developing embedded computing and data processing solutions for national security applications at LLNL.

Michael Perrone IBM Research Division, Thomas J. Watson Research Center, P.O. Box 218, Yorktown Heights, New York 10598 (mppus.ibm.com). Dr. Perrone is an IBM Master Inventor and the manager of the Cell/B.E. Solutions department, which has the mission of identifying and optimizing high-affinity workloads for the Cell/B.E. and other multicore processors. Current projects include high-performance computing workloads, seismic imaging, network intrusion detection, digital content creation, rich media mining, image analysis, speech recognition, and bioinformatics. He received a Ph.D. degree in physics from Brown University. His research includes algorithmic optimization for the Cell/B.E. processor, parallel computing, and statistical machine learning.

Bořivoj Tydlitát IBM Czech Republic, Voice Technologies and Systems, V Parku 2294/4, 148 00 Praha 4, Czech Republic (borivoj_tydlitatcz.ibm.com). Mr. Tydlitát received an M.S. degree in computer engineering from the Czech Technical University, Prague. He has worked at the IBM Thomas J. Watson Research Center on multiple projects related to speech recognition and natural language understanding. He is currently a member of the IBM Research team in Prague, working on the development of embedded IBM ViaVoice* speech recognition software and participating in speech technology research.

Ashwini K. Nanda IBM Research Division, Thomas J. Watson Research Center, P.O. Box 218, Yorktown Heights, NY 10598 (ashwinius.ibm.com). As the Chief Architect of Quasar/Cell/B.E. systems, Dr. Nanda established and managed the Quasar systems team in the IBM Systems and Technology group. He played a lead role in establishing the Cell/B.E./Quasar systems technology, product roadmap (including QS20, the first Cell/B.E. blade product), and business to focus on the emerging compute-intensive, streaming, real-time, and interactive applications. Prior to that, Dr. Nanda led research and prototyping of Cell/B.E. processor–based systems and their application at the IBM T.J. Watson Research Center, in Yorktown Heights, New York. Earlier at IBM Research, he established and managed the Scalable Server Architecture group for several years. His key research contributions include MemorIES (Memory Instrumentation and Emulation System) and High Throughput Coherence Controllers. Dr. Nanda was co-General Chair of the International Symposium on High Performance Computer Architecture (HPCA-7), he served on the editorial board of IEEE Transactions on Parallel and Distributed Systems, and he co-edited a special issue of the IEEE Computer magazine. He holds ten U.S. patents and has published more than 40 papers on computer systems architecture, design, and performance.

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