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IBM Journal of Research and Development
Cell Broadband Engine Technology and Systems   Volume 51, Number 5, 2007
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Microarchitecture and implementation of the synergistic processor in 65-nm and 90-nm SOI - References

 by B. Flachs,
S. Asano,
S. H. Dhong,
H. P. Hofstee,
G. Gervais,
R. Kim,
T. Le,
P. Liu,
J. Leenstra,
J. S. Liberty,
B. Michael,
H.-J. Oh,
S. M. Mueller,
O. Takahashi,
K. Hirairi,
A. Kawasumi,
H. Murakami,
H. Noro,
S. Onishi,
J. Pille,
J. Silberman,
S. Yong,
A. Hatakeyama,
Y. Watanabe,
N. Yano,
D. A. Brokenshire,
M. Peyravian,
V. To,
and E. Iwata
References

  1. B. Flachs, S. Asano, S. H. Dhong, H. P. Hofstee, G. Gervais, R. Kim, T. Le, et al., “The Microarchitecture of the Synergistic Processor for a Cell Processor,” IEEE J. Solid State Circuits 41, No. 1, 63–70 (2006).
  2. O. Takahashi, R. Cook, S. Cottier, S. H. Dhong, B. Flachs, K. Hirairi, A. Kawasumi, et al., “The Circuits and Physical Design of the Synergistic Processor Element of a Cell Processor,” Proceedings of the Symposium on VLSI Circuits, Kyoto, Japan, 2005, pp. 20–23.
  3. J. A. Kahle, M. N. Day, H. P. Hofstee, C. R. Johns, T. R. Maeurer, and D. Shippy, “Introduction to the Cell Multiprocessor,” IBM J. Res. & Dev. 49, No. 4/5, 589–604 (July/September 2005).
  4. Synergistic Processor Unit Instruction Set Architecture, Version 1.2, IBM Corporation, Sony Computer Entertainment Corporation, and Toshiba Corporation; see http://www.ibm.com/chips/techlib/techlib.nsf/techdocs/76CA6C7304210F3987257060006F2C44/$file/SPU_ISA_v1.2_27Jan2007_pub.pdf.
  5. V. Srinivasan, D. Brooks, M. Gschwind, P. Bose, V. Zyuban, P. N. Strenski, and P. G. Emma, “Optimizing Pipelines for Power and Performance,” Proceedings of the 35th Annual ACM/IEEE International Symposium on Microarchitecture, Istanbul, Turkey, 2002, pp. 333–344.
  6. S. H. Dhong, O. Takahashi, M. White, T. Asano, T. Nakazato, J. Silberman, A. Kawasumi, and H. Yoshihara, “A 4.8GHz Fully Pipelined Embedded SRAM in the Streaming Processor of a Cell Processor,” Proceedings of the IEEE International Solid-State Circuits Conference, San Francisco, CA, 2005, pp. 486–487.
  7. N. Mäding, J. Leenstra, J. Pille, R. Sautter, S. Büttner, S. Ehrenreich, and W. Haller, “The Vector Fixed Point Unit of the Synergistic Processor Element of the Cell Architecture Processor,” Proceedings of the Conference on Design, Automation and Test in Europe: Designers' Forum, Munich, Germany, 2006, pp. 244–248.
  8. A. E. Eichenberger, J. K. O'Brien, K. M. O'Brien, P. Wu, T. Chen, P. H. Oden, D. A. Prener, et al., “Using Advanced Compiler Technology to Exploit the Performance of the Cell Broadband Engine™ Architecture,” IBM Syst. J. 45, No. 1, 59–84 (2006).
  9. A. E. Eichenberger, K. O'Brien, K. O'Brien, P. Wu, T. Chen, P. H. Oden, D. A. Prener, et al., “Optimizing Compiler for a Cell Processor,” Proceedings of the 14th International Conference on Parallel Architectures and Compilation Techniques (PACT), Saint Louis, MO, 2005, pp. 161–172.
  10. S. Williams, J. Shalf, L. Oliker, S. Kamil, P. Husbands, and K. Yelick, “The Potential of the Cell Processor for Scientific Computing,” Proceedings of the 3rd Conference on Computing Frontiers, Ischia, Italy, 2006, pp. 9–20.
  11. IBM Corporation (September 2, 2002). IBM to Build World's First Cell Broadband Engine Based Supercomputer. Press release; see http://www-03.ibm.com/press/us/en/pressrelease/20210.wss.
  12. H.-J. Oh, S. M. Mueller, C. Jacobi, K. D. Tran, S. R. Cottier, B. W. Michael, H. Nishikawa, et al., “A Fully Pipelined Single-Precision Floating-Point Unit in the Synergistic Processor Element of a Cell Processor,” IEEE J. Solid-State Circuits 41, No. 4, 759–771 (2006).
  13. R. Chaudhry, D. Stasiak, S. Posluszny, and S. Dhong, “A Cycle Accurate Power Estimation Tool,” Proceedings of the Asia and South Pacific Conference on Design Automation, Yokohama, Japan, 2006, pp. 867–870.


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