Brian Flachs IBM Systems and Technology Group, 11400 Burnet Road, Austin, Texas 78758 (flachsus.ibm.com). Dr. Flachs served as architect, microarchitect and unit logic leader for the SPU team. He is interested in low-latency–high-frequency processors. Dr. Flachs received a B.S.E.E. degree from New Mexico State University and M.S. and Ph.D. degrees from Stanford University.

Shigehiro Asano Toshiba Corporation, 1, Komukai-Toshiba-Cho, Saiwai-Ku, Kawasaki 212-8582, Japan. Mr. Asano is a Senior Research Scientist. He has an M.S. degree in information engineering from the Tokyo Institute of Technology, Japan. His research interests include parallel processing, media processors, and reconfigurable processors. Mr. Asano is a member of the IEEE and the IEEE Computer Society.

Sang H. Dhong IBM Systems and Technology Group, 11400 Burnet Road, Austin, Texas 78758 (dhongus.ibm.com). Dr. Dhong received a B.S.E.E. degree from Korea University and M.S. and Ph.D. degrees in electrical engineering from the University of California at Berkeley. He joined the IBM Research Division in 1983 as a Research Staff Member and became the chief technologist of the Austin Research Laboratory in 1999. In 2000, he joined the Sony–Toshiba–IBM (STI) Design Center as one of the key leaders, primarily concentrating primarily on an 11-FO4 coprocessor design. He is an IBM Distinguished Engineer, a member of the IBM Academy of Technology, and a Fellow of IEEE. He holds more than 125 U.S. patents. Dr. Dhong has received four IBM Outstanding Innovation and Technical Achievement Awards.

H. Peter Hofstee IBM Systems and Technology Group, STI Design Center, 11400 Burnet Road, Austin, Texas 78758 (hofsteeus.ibm.com). Dr. Hofstee received his doctorandus degree in theoretical physics from the Rijks Universiteit Groningen, The Netherlands, in 1988, and his M.S. and Ph.D. degrees in computer science from the California Institute of Technology in 1991 and 1994, respectively. After two years on the faculty at Caltech, in 1996 he joined the IBM Austin Research Laboratory, where he participated in the design of two 1-GHz PowerPC prototypes, focusing on microarchitecture, logic design, and chip integration. In 2000 he helped start the Sony–Toshiba–IBM Design Center to design a next generation of processors for the broadband era, the Cell/B.E. processor. Dr. Hofstee is a member of the Cell/B.E. Architecture team, and he is the Chief Architect of the synergistic processor in the Cell/B.E. processor. He was elected to the IBM Academy of Technology in 2004.

Gilles Gervais IBM Systems and Technology Group, 11400 Burnet Road, Austin, Texas 78758. Mr. Gervais received a B.S. degree in electrical engineering from Drexel University. He joined the IBM Federal Systems Division in 1982, moving to the IBM Austin Research Laboratory in 1994. He was the design leader for the Altivec engine of the Apple G5 processor. Mr. Gervais is currently the manager of the SPE verification and logic design teams for the Cell/B.E. processor.

Roy Kim IBM Systems and Technology Group, 11400 Burnet Road, Austin, Texas 78758 (roykimus.ibm.com). Mr. Kim received a B.S. degree in electrical engineering from the State University of New York at Stony Brook and an M.S. degree in computer engineering from Syracuse University. He has worked on many hardware development projects in chip, card, and systems design. Mr. Kim most recently worked on the Cell/B.E. processor design at the STI Design Center.

Tien Le IBM Systems and Technology Group, 11400 Burnet Road, Austin, Texas 78758. Mr. Le served as the verification leader for the SMF unit. He received a B.S. degree in electrical and electronics engineering, mathematics, and computer science and an M.S. degree in mathematics, both from California State Polytechnic University. Mr. Le joined the STI team in 2002 and is working on the follow-on project.

Peichun Liu IBM Systems and Technology Group, 11400 Burnet Road, Austin, Texas 78758. Mr. Liu received a B.S.E.E. degree from the National Taiwan Ocean University and an M.S.E.E. degree from the University of Texas at Arlington. He joined IBM in 1991 and worked on POWER3*, POWER4*, and Cell/B.E. microprocessor design projects.

Jens Leenstra IBM Systems and Technology Group, IBM Deutschland Entwicklung GmbH, Schoenaicherstrasse 220, D-71032 Boeblingen, Germany (leenstrade.ibm.com). Dr. Leenstra received an M.S. degree from the University of Twente, The Netherlands, and a Ph.D. degree from the University of Eindhoven, The Netherlands, joining IBM at Boeblingen in 1994. He has worked in several areas of the Server Group and the Systems and Technology Group development organization, including logic design and verification of I/O chips, multiprocessor system verification of the G2 and G3 mainframe computers, the Cell/B.E. processor SPEs, and the POWER6* VMX unit. He is currently working on next-generation IBM microprocessors. Dr. Leenstra's current interests focus on computer architecture, high-frequency design, low power, and design for testability.

John S. Liberty IBM Systems and Technology Group, 11501 Burnet Road, Austin, Texas 78758. Mr. Liberty received B.S. and M.S. degrees in electrical engineering from North Carolina State University. He is an advisory engineer in the Sony–Toshiba–IBM (STI) Design Center, responsible for helping architect and develop the Cell Broadband Engine. His main focus within the Cell/B.E. processor is the SPU SIMD processor. He was a leader in designing the SPU channel interface and the SPU inherent security architecture. Before working on the Cell/B.E. processor, he was a designer working on graphic processing units. Mr. Liberty holds four patents, with 12 patents pending, he has co-authored three technical articles.

Brad Michael IBM Systems and Technology Group, 11400 Burnet Road, Austin, Texas 78758. Mr. Michael received a B.S. degree in computer engineering from Iowa State University in 1989. He joined IBM that same year and is now involved in microprocessor logic design in the STI Design Center.

Hwa-Joon Oh IBM Systems and Technology Group, 11400 Burnet Road, Austin, Texas 78758 (hjohus.ibm.com). Dr. Oh received B.S and M.S. degrees from Yonsei University, Korea, and a Ph.D. degree from Michigan State University. In 1998, he joined the IBM Austin Research Laboratory, where he worked on POWER4 microprocessor design. He is currently working with the STI Design Center, where he is involved in architecture, logic, circuits, and physical implementations of Cell/B.E. microprocessor. His main research area is artificial neural network, SRAM and DRAM design, and broadband microprocessor design. Dr. Oh has authored or co-authored several journal papers and patents.

Silvia Melitta Mueller IBM Systems and Technology Group, IBM Deutschland Entwicklung GmbH, Schoenaicherstrasse 220, D-71032 Boeblingen, Germany (smmde.ibm.com). Dr. Mueller is a Senior Technical Staff Member in the high-performance processor design team. She received B.S. degrees in mathematics and computer science, an M.S. degree in mathematics, and a Ph.D. degree in computer science from the University of Saarland, Germany. Dr. Mueller held a postdoctoral position at Berkeley and spent two short sabbaticals at the computer science department of the Massachusetts Institute of Technology. In 1998, she became a Privatdozent at the computer science department of the University of Saarland and still holds a teaching assignment there. Dr. Mueller joined IBM at Boeblingen in late 1999. From 2001 to 2003 she was on international assignment to IBM Austin, joining the STI Design Center developing the Cell/B.E. processor. She led the development of the floating-point units for the Cell/B.E. processor and for the POWER6 VMX.

Osamu Takahashi IBM Systems and Technology Group, 11400 Burnet Road, Austin, Texas 78758 (osamuus.ibm.com). Dr. Takahashi is a Senior Technical Staff Member and manager of the circuit design team for the SPE developed at the STI Design Center. He received a B.S. degree in engineering physics and an M.S. degree in electrical engineering from the University of California at Berkeley, as well as a Ph.D. degree in computer and mathematical sciences from Tohoku University, Japan.

Koji Hirairi Sony Corporation, Atsugi Technology Center, 4-14-1 Asahi-cho, Atsugi-shi, Kanagawa 243-0014 Japan. Mr. Hirairi was in charge of research and development of the custom datapath macro at the STI Design Center. He received B.S. and M.S. degrees in electronics engineering from Chuo University, Japan and is currently involved in DRAM and I/O circuit design.

Atsushi Kawasumi Toshiba Corporation, 580-1, Horikawa-Cho, Saiwai-Ku, Kawasaki, 212-8520, Japan. Mr. Kawasumi received B.S. and M.S. degrees in pure and applied sciences from the University of Tokyo. He joined the Toshiba Semiconductor Device Engineering Laboratory in 1991, where he engaged in research and development of ultrahigh-speed SRAM. He moved to Toshiba America Electronic Components, Inc., in 2002 to join the STI Cell/B.E. processor project. Mr. Kawasumi is currently with the Center for Semiconductor Research and Development, Semiconductor Company, Toshiba Corporation.

Hiroaki Murakami Toshiba Corporation, 580-1, Horikawa-Cho, Saiwai-Ku, Kawasaki 212-8520, Japan. Mr. Murakami received a B.S. degree in mathematical engineering from the University of Osaka Prefecture, Japan. He joined the Toshiba Corporation in 1982 and worked on developing RISC and Cell/B.E. processors. He is currently with the Broadband System LSI Development Center, Semiconductor Company, Toshiba Corporation.

Hiromi Noro Toshiba America Electronic Components, 9696 N. Mopac Highway, Austin, Texas 78759. Mr. Noro is a design engineering manager. He received a B.S. degree in electronics communication engineering and an M.S. degree in electrical engineering, both from Tokai University, Japan. Mr. Noro's research interests include the design of various types of high-speed custom circuits for microprocessors and of high-speed memory (SRAM, register file, and content-addressable memory) for microprocessors.

Shoji Onishi IBM Engineering and Technology Service, IBM Japan, 800 Ichimiyake, Yasu-shi, Shiga 520-2392, Japan. In 1990, Mr. Onishi joined the IBM Yasu Technology Application Laboratory, where he was involved in the design of hard disk controllers, SRAM, and DRAM. He was assigned to the IBM Austin Research Laboratory in 1996 to design the 1-GHz eDRAM macro. Mr. Onishi has been involved in the research and development of high-speed custom array macros of the SPE in the STI Design Center since 2001.

Juergen Pille IBM Systems and Technology Group, IBM Deutschland Entwicklung GmbH, Schoenaicherstrasse 220, D-71032 Boeblingen, Germany (pillejde.ibm.com). Mr. Pille is a Senior Technical Staff Member. He received an M.S. degree in microelectronics from Hanover University, Germany. Since joining IBM in 1990, he has worked on various microprocessor designs, focusing on arrays and circuits, most recently a first-generation Cell/B.E. processor. Mr. Pille is currently working on Cell/B.E. processor core array designs.

Joel Silberman IBM Research Division, Thomas J. Watson Research Center, P.O. Box 218, Yorktown Heights, New York 10598 (lberus.ibm.com). Dr. Silberman is a Research Staff Member. He received a Ph.D. in electrical engineering from Stanford University in 1986 and joined the IBM Research Division that same year. He has worked on numerous research and product-oriented microprocessor design projects focusing on high-speed and low-power designs. Dr. Silberman's current work is concerned with tradeoffs in microarchitecture and circuit performance of advanced cache memory and instruction issue logic.

Suksoon Yong IBM Systems and Technology Group, 11400 Burnet Road, Austin, Texas 78758. Mr. Yong received a B.S. degree in electronics engineering from Korea University and an M.S. degree from the University of Michigan. Since joining IBM in 1990, he has been working on ASIC and microprocessor logic designs and system-on-chip ASIC integration and logic design. Mr. Yong is currently the SPE timing leader in the STI Design Center.

Akiyuki Hatakeyama Sony Computer Entertainment, Inc., Tokyo, Japan. Mr. Hatakeyama received B.S. and M.S. degrees in computer science from the Kanagawa Institute of Technology, Japan. He is currently involved in developing the Sony PLAYSTATION† system.

Yukio Watanabe Toshiba Corporation, 580-1, Horikawa-Cho, Saiwai-Ku, Kawasaki 212-8520, Japan. Mr. Watanabe received a B.E. degree in electronic engineering from Tohoku University, Japan, in 1993, and an M.E. degree in information science from the Graduate School of Information Sciences, Tohoku University, Japan. He joined the Toshiba Corporation in 1995, where he has been engaged in the design and development of high-performance microprocessors. From 2001 to 2005 he was assigned to the STI Design Center where he was engaged in the development of the Cell/B.E. processor.

Naoka Yano Toshiba Corporation, 580-1, Horikawa-Cho, Saiwai-Ku, Kawasaki 212-8520, Japan. Ms. Yano received a B.S. degree in pure and applied sciences from the University of Tokyo. She joined the Semiconductor Device Engineering Laboratory, Toshiba Corporation, in 1991. She was engaged in the research and development of high-performance microprocessors. In 2001, she moved to Toshiba America Electronic Components, Inc., and was involved in the development of the Cell/B.E. processor. Ms. Yano is currently with the Broadband System LSI Development Center, Semiconductor Company, Toshiba Corporation.

Daniel A. Brokenshire IBM Systems and Technology Group, 11400 Burnet Road, Austin, Texas 78758 (brokenshus.ibm.com). Mr. Brokenshire is a Senior Technical Staff Member with six years of experience in the Cell/B.E. Processor Design Center. He currently serves as a senior member of the IBM Cell Processor Systems Enablement team working on the Cell/B.E. Software Development Kit. His responsibilities include the development of programming standards, language extensions, reusable software libraries, and software documentation. Mr. Brokenshire received a B.S. degree in computer science and B.S. and M.S. degrees in electrical engineering, all from Oregon State University. Prior to his work on the Cell/B.E. processor, he enjoyed a productive career developing 3D graphics products for Tektronix, Inc., and IBM.

Mohammad Peyravian IBM Systems and Technology Group, 3039 Cornwallis Road, P.O. Box 12195, Research Triangle Park, North Carolina 27709 (peyravnus.ibm.com). Dr. Peyravian received a Ph.D. degree in electrical engineering from the Georgia Institute of Technology. He is a network processor architect whose interests include networking, network processors, cryptography, and security. Dr. Peyravian has published more than 40 journal and conference papers; he holds more than 30 patents in networking, cryptography, and security.

VanDung To IBM Systems and Technology Group, 11400 Burnet Road, Austin, Texas 78758. Ms. To received a B.A. degree in computer science from Rice University. She is currently working on an M.B.A. degree at the University of Texas at Austin. Ms. To joined IBM in 2001 and is now working on Cell/B.E. processor software development.

Eiji Iwata Sony Computer Entertainment, Inc., Tokyo, Japan (Eiji.Iwatajp.sony.com). Mr. Iwata received an M.E. degree in information systems engineering from Kyushu University, Japan. He joined Sony Corporation, Tokyo, in 1991. In 1996, he was a visiting researcher at the Hydra project in the Computer Science Laboratory at Stanford University. Returning to Sony, he worked on the development of a chip multiprocessor for media applications. He joined the STI Design Center in 2001, and he currently works on a project promoting the Cell/B.E. processor.

*Trademark, service mark, or registered trademark of International Business Machines Corporation in the United States, other countries, or both.
†Cell Broadband Engine and PLAYSTATION are trademarks of Sony Computer Entertainment, Inc., in the United States, other countries, or both.