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IBM System z9 eFUSE applications and methodology - References
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by R. F. Rizzolo,
T. G. Foote,
J. M. Crafts,
D. A. Grosch,
T. O. Leung,
D. J. Lund,
B. L. Mechtly,
B. J. Robbins,
T. J. Slegel,
M. J. Tremblay,
and G. A. Wiedemeier
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P. Bunce, J. Davis, T. Knips, and D. Plass, “System for Implementing a Column Redundancy Scheme for Arrays with Controls that Span Multiple Data Bits,” U.S. Patent 6,584,023, June 24, 2003.
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T. H. Daubenspeck, T. L. McDevitt, W. T. Motsiff, and A. K. Stamper, “Triple Damascene Fuse,” U.S. Patent 6,667,533, December 2003.
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C. Kothandaraman, S. K. Iyer, and S. S. Iyer, “Electrically Programmable Fuse (eFUSE) Using Electromigration in Silicides,” IEEE Electron Device Lett. 23, No. 9, 523–525 (2002).
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Y. Lee, S. Jacobs, S. Stader, N. Mielke, and R. Nachman, “The Impact of PMOST Bias-Temperature Degradation on Logic Circuit Reliability Performance,” Microelectron. Reliabil. 45, 107–114 (2005).
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D. M. Berger, J. Y. Chen, F. D. Ferraiolo, J. A. Magee, and G. A. Van Huben, “High-Speed Source-Synchronous Interface for the IBM System z9 Processor,” IBM J. Res. & Dev. 51, No. 1/2, 53–64 (2007, this issue).
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O. Torreiter, U. Baur, G. Geocke, and K. Melocco, “Testing the Enterprise IBM System/390* Multi Processor,” Proceedings of the IEEE International Test Conference, 1997, pp. 115–123.
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T. Foote, D. Hoffman, W. Huott, T. Koprowski, B. Robbins, and M. Kusko, “Testing the 400MHz IBM Generation-4 CMOS Chip,” Proceedings of the IEEE International Test Conference, 1997, pp. 106–114.
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M. R. Ouellette, D. L. Anand, and P. Jakobsen, “Shared Fuse Macro for Multiple Embedded Memory Devices with Redundancy Compression Scheme,” Proceedings of the Custom Integrated Circuits Conference, 2001, pp. 191–194.
*Trademark, service mark, or registered trademark of International Business Machines Corporation in the United States, other countries, or both.
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