Daniel J. Poindexter IBM Systems and Technology Group, 2070 Route 52, Hopewell Junction, New York 12533 (poindextus.ibm.com). Mr. Poindexter is a Senior Technical Staff Member in the IBM 300-mm characterization organization. He received a B.S. degree in mechanical engineering from Carnegie Mellon University in 1982 and joined IBM at the Burlington, Vermont, facility that same year. He received an M.S. degree in electrical engineering from Rensselaer Polytechnic Institute in 1990. Mr. Poindexter received an IBM Outstanding Technical Achievement Award for his work on implementing 90-nm chip technology for zSeries and pSeries* computers; he continues this work for the 65-nm generation.

Scott R. Stiffler IBM Systems and Technology Group, 2070 Route 52, Hopewell Junction, New York 12533 (sstiffleus.ibm.com). Mr. Stiffler is currently a Distinguished Engineer in the IBM Semiconductor Research and Development Center in East Fishkill, New York. He received a Ph.D. degree in materials science from Cornell University and has worked for IBM since 1982 in both the Research and Microelectronics Divisions. Throughout his career, his primary focus has been on semiconductor process development from inception to product qualification.

Philip T. Wu IBM Systems and Technology Group, 2070 Route 52, Hopewell Junction, New York 12533 (ptwuus.ibm.com). Mr. Wu is a Senior Technical Staff Manager in the IBM 300-mm characterization organization. He received a B.S. degree in electrical engineering from the University of Michigan in 1974, an M.S. degree in electrical engineering from Stanford University in 1976, an M.B.A. degree from Rensselaer Polytechnic Institute in 1994, and Project Management Institute certification in 2001. He joined IBM in 1976 and has since worked in advanced VLSI design, test, and characterization. He received four IBM Outstanding Technical Achievement Awards for his work on zSeries technology development. Mr. Wu has received three IBM Invention Achievement Awards; he holds seven U.S. patents.

Paul D. Agnello IBM Systems and Technology Group, 2070 Route 52, Hopewell Junction, New York 12533 (agnellopus.ibm.com). Dr. Agnello received his B.S., M.S., and Ph.D. degrees from the Electrical, Computer, and Systems Engineering Department of Rensselaer Polytechnic Institute. He joined the IBM Thomas J. Watson Research Center in 1988 and the IBM Technology Group in 1992. During his career at IBM, he has worked on low-temperature CVD processing of Si and SiGe epi and selective epi, Co and Ti alloy silicide development, 0.25-μm-node device integration, and 180-nm-node Cu BEOL integration. He managed the device integration group responsible for bringing the IBM 130-nm and 90-nm SOI CMOS technologies to market and was named an IBM Distinguished Engineer in 2003. Currently he manages the high-performance CMOS integration and device project responsible for the 45-nm-node high-performance logic technology. Dr. Agnello is the author or co-author of more than 60 publications; he holds more than 15 U.S. patents.

Thomas Ivers IBM Systems and Technology Group, 2070 Route 52, Hopewell Junction, New York 12533 (iverstus.ibm.com).

Shreesh Narasimha IBM Systems and Technology Group, 2070 Route 52, Hopewell Junction, New York 12533 (snarasus.ibm.com).

Thomas B. (Tom) Faure IBM Systems and Technology Group, 1000 River Street, Essex Junction, Vermont 05452 (tfaureus.ibm.com). After receiving a B.S. degree in chemical engineering from Clarkson University in 1986, Mr. Faure joined IBM at the Burlington, Vermont, facility to work on photomask development. He is currently a Senior Technical Staff Member working on advanced photomask development and manufacturing. He is an author or co-author of 15 patents and six technical papers.

Jed H. Rankin IBM Systems and Technology Group, 1000 River Street, Essex Junction, Vermont 05452 (rankinjhus.ibm.com). Mr. Rankin received a B.S. degree in chemical engineering from Clarkson University in 1995 prior to joining the IBM Burlington, Vermont, Technology Development Group; he recently received a master's degree in business administration from Phoenix University. At IBM he has been responsible for reactive ion etching (RIE) development, optical proximity correction (OPC) generation lithography development, and process integration. He is currently a Senior Engineer focusing on 90-nm integration and infrastructural optimization. Mr. Rankin holds more than 70 patents; he has industry publications on ACLV optimization, process migration, and mask process improvement.

David A. Grosch IBM Systems and Technology Group, 1000 River Street, Essex Junction, Vermont 05452 (groschus.ibm.com). Mr. Grosch received a B.S. degree in electrical engineering from the Rochester Institute of Technology in 1985, joining IBM that same year. He is currently an Advisory Engineer working on zSeries burn-in development.

Marc D. Knox IBM Systems and Technology Group, 1000 River Street, Essex Junction, Vermont 05452 (marcknoxus.ibm.com). Mr. Knox received a B.S. degree in electrical engineering from the State University of New York and an M.S. degree in manufacturing systems engineering from Rensselaer Polytechnic Institute. He is a test development engineer working at the IBM facility in Essex Junction, Vermont, involved in multiple aspects of test and burn-in development engineering. Mr. Knox holds a number of patents and patents pending related to test and burn-in.

Daniel C. Edelstein IBM Research Division, Thomas J. Watson Research Center, P.O. Box 218, Yorktown Heights, New York 10598 (edelsteius.ibm.com). Dr. Edelstein is an IBM Fellow and Manager of BEOL Technology Strategy at the IBM Thomas J. Watson Research Center. He received his B.S., M.S., and Ph.D. degrees in applied physics from Cornell University for work on ultrafast quantum electronics. At IBM, he has worked since 1989 on advanced on-chip (ULSI) interconnect technologies and System-on-Package concepts, spanning the range of interconnect technical and physical aspects. Overall, he has led teams to apply these to the innovation and implementation of Cu and Cu/Low-k on-chip interconnect technologies for IBM integrated circuit chips. Dr. Edelstein played a leadership role in the IBM industry-first “Cu chip” technology, and more recently in the introduction of the IBM Cu/SiCOH low-k BEOL. He currently leads strategic projects on future enhancements to these technologies. He holds 76 U.S. patents and has received numerous technical, publication, and corporate awards. As coinventor, one of his patents was awarded Inventor of the Year 2006 by the New York State Intellectual Property Law Association. In May 2006, he was appointed an IBM Fellow for his career contributions to ULSI interconnect technologies.

Mukesh Khare IBM Research Division, Thomas J. Watson Research Center, P.O. Box 218, Yorktown Heights, New York 10598 (kmukeshus.ibm.com). Dr. Khare received the M.Tech. degree from the IIT–Bombay, India, in 1994 and the M.S., M. Phil., and Ph.D. degrees from Yale University in 1995, 1997, and 1999 respectively. In 1998 he joined the IBM Semiconductor Research and Development Center in Hopewell Junction, New York, and has been actively pursuing research and development in CMOS technology since then. As the FEOL integrator, he led the development of 90-nm SOI technology. He is currently a Senior Manager leading 32-nm silicon technology research at the Thomas J. Watson Research Center. Dr. Khare's research interests include the development of advanced devices and structures for CMOS technology, process integration, SRAM and device reliability for acceptable operating voltage, gate dielectric development, and technology/design interaction.

Gary B. Bronner IBM Systems and Technology Group, 2070 Route 52, Hopewell Junction, New York 12533 (gbronnerus.ibm.com). Dr. Bronner is a Distinguished Engineer at IBM and Project Leader for the IBM SOI Development Alliance. Since 2004 he has been responsible for the research and development of the IBM 90-nm, 65-nm, and 45-nm SOI technologies, which are used for IBM internal microprocessors and the processors of selected partners. He was previously in charge of the IBM DRAM Development Alliance and led the development of IBM DRAM technology from the 0.25-μm generation through the 0.11-μm generation. The technology he developed continues to be used worldwide by all DRAM vendors using trench capacitor DRAM technology and internally in IBM for embedded DRAM products. Dr. Bronner received a B.S. degree in electrical engineering from Brown University and M.S. and Ph.D. degrees from Stanford University. He is a Fellow of the IEEE. He has reached the 23rd IBM Invention Achievement Plateau, with 64 patents issued.

Hyun-Jang Nam IBM Systems and Technology Group, 2070 Route 52, Hopewell Junction, New York 12533 (hjnamus.ibm.com).

Shahid A. Butt IBM Systems and Technology Group, 2070 Route 52, Hopewell Junction, New York 12533 (sbuttus.ibm.com). After receiving his M.S. degree in materials science and engineering from the Rochester Institute of Technology, Mr. Butt joined Infineon Technologies Incorporated, working in the area of lithography development. In 2003, he joined the 300-mm lithography group at IBM and worked on the introduction and subsequent support of the lithography process for the 90-nm technology. He is currently working on 45-nm logic process development.

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