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IBM Journal of Research and Development
IBM System z9   Volume 51, Number 1/2, 2007
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Design methods for attaining IBM System z9 processor cycle-time goals - References

 by G. Mayer,
G. Doettling,
R. F. Rizzolo,
C. J. Berry,
S. M. Carey,
C. M. Carney,
J. Keinert,
P. Loeffler,
W. Nop,
D. E. Skooglund,
V. A. Victoria,
A. P. Wagstaff,
and P. M. Williams
References

  1. D. M. Berger, J. Y. Chen, F. D. Ferraiolo, J. A. Magee, and G. A. Van Huben, “High-Speed Source-Synchronous Interface for the IBM System z9 Processor,” IBM J. Res. & Dev. 51, No. 1/2, 53–64 (2007, this issue).
  2. P. Mak, G. E. Strait, M. A. Blake, K. W. Kark, V. K. Papazova, A. E. Seigler, G. A. Van Huben, L. Wang, and G. C. Wellwood, “Processor Subsystem Interconnect Architecture for a Large Symmetric Multiprocessing System,” IBM J. Res. & Dev. 48, No. 3/4, 323–337 (2004).
  3. R. M. Averill III, K. G. Barkley, M. A. Bowen, P. J. Camporese, A. H. Dansky, R. F. Hatch, D. E. Hoffman, et al., “Chip Integration Methodology for the IBM S/390* G5 and G6 Custom Microprocessors,” IBM J. Res. & Dev. 43, No. 5/6, 681–706 (l999).
  4. N. Kimizuka, T. Yamamoto, T. Mogami, K. Yamaguchi, K. Imai, and T. Horiuchi, “Impact of Bias Temperature Instability for Direct Tunneling Ultrathin Gate Oxide on MOSFET Scaling,” Symposium on VLSI Technology, Digest of Technical Papers,, Kyoto, Japan, 1999, pp. 73–74.
  5. G. Chen, M. F. Li, C. H. Ang, J. Z. Zheng, and D. L. Kwong, “Dynamic NBTI of p-MOS Transistors and Its Impact on MOSFET Scaling,” IEEE Electron Device Lett. 23, No. 12, 734–736 (2002).
  6. D. Schroder and J. F. Babcock, “Negative Bias Temperature Instability: Road to Cross in Deep Submicron Silicon Semiconductor Manufacturing,” J. Appl. Phys. 94, No. 1, 11–18 (2003).
  7. C. Visweswariah and A. R. Conn, “Formulation of Static Circuit Optimization with Reduced Size, Degeneracy and Redundancy by Timing Graph Manipulation,” ACM/IEEE International Conference on Computer-Aided Design (ICCAD), Digest of Technical Papers,, November 1999, pp. 244–251.
  8. A. R. Conn, I. M. Elfadel, W. W. Molzen, Jr., P. R. O'Brien, P. N. Strenski, C. Visweswariah, and C. B. Whan, “Gradient-Based Optimization of Custom Circuits Using a Static-Timing Formulation,” IEEE Design Automation Conference, Digest of Technical Papers,, June 1999, pp. 452–459.
  9. S. Wolpin, IBM Research Division, “Chip Checker”; see http://domino.watson.ibm.com/comm/wwwr_thinkresearch.nsf/pages/20020625_einstuner.html.
  10. P. Restle, IBM Research Division, “EinsTuner Animations”; see http://www.research.ibm.com/da/animation/index.html.
  11. A. Wächter, “An Interior Point Algorithm for Large-Scale Nonlinear Optimization with Applications in Process Engineering,” Ph.D. Thesis, Carnegie Mellon University, Pittsburgh, PA, 2002; see http://www.research.ibm.com/people/a/andreasw/.
  12. A. Wächter, C. Visweswariah, and A. R. Conn, “Large-Scale Nonlinear Optimization in Circuit Tuning,” Future Generation Computer Syst. 21, No. 8, 1251–1262 (2005).
  13. “Interior Point OPTimizer,” Wikipedia; see http://en.wikipedia.org/wiki/IPOPT.
  14. B. W. Curran, Y. H. Chan, P. T. Wu, P. J. Camporese, G. A. Northrop, R. F. Hatch, L. B. Lacey, J. P. Eckhardt, D. T. Hui, and H. H. Smith, “IBM eServer* z900 High-Frequency Microprocessor Technology, Circuits, and Design Methodology,” IBM J. Res. & Dev. 46, No. 4/5, 631–644 (2002).
  15. V. B. Rao, J. P. Soreff, T. B. Brodnax, and R. E. Mains, “EinsTLT: Transistor-Level Timing with EinsTimer,” Proceedings of the ACM/IEEE 1999 International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (Tau-99),, Monterey, CA, March 8–9, 1999, pp. 1–6.
  16. T. J. Slegel, E. Pfeffer, and J. A. Magee, “The IBM eServer z990 Microprocessor,” IBM J. Res. & Dev. 48, No. 3/4, 295–309 (2004).
  17. R. F. Rizzolo, G. Hinkel, S. Michnowski, T. J. McPherson, and A. J. Sutcliffe, “System Performance Management for the S/390 Parallel Enterprise Server* G5,” IBM J. Res. & Dev. 43, No. 5/6, 651–660 (1999).
  18. D. J. Poindexter, S. R. Stiffler, P. T. Wu, P. D. Agnello, T. Ivers, S. Narasimha, T. B. Faure, et al., “Optimization of Silicon Technology for the IBM System z9,” IBM J. Res. & Dev. 51, No. 1/2, 5–18 (2007, this issue).

*Trademark, service mark, or registered trademark of International Business Machines Corporation in the United States, other countries, or both.

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