Guenter Mayer IBM Systems and Technology Group, IBM Deutschland Entwicklung GmbH, Schoenaicherstrasse 220, 71032 Boeblingen, Germany (guenter_mayerde.ibm.com). Mr. Mayer is a Senior Engineer in the IBM Systems and Technology Group, Boeblingen, Germany. He joined IBM in 1994 and has worked on several generations of System z microprocessors as a key designer and technical leader. He is recognized as a global expert in the field of high-performance circuit design and microprocessor design. Mr. Mayer received a master's degree in electrical engineering from the University of Stuttgart, Germany.

Gerhard Doettling IBM Systems and Technology Group, IBM Deutschland Entwicklung GmbH, Schoenaicherstrasse 220, 71032 Boeblingen, Germany (gdoettlide.ibm.com). Mr. Doettling is a Senior Engineer, currently working in the IBM Hardware Development Laboratory in Poughkeepsie, New York. He was responsible for the System z9 CP core logic design and the CP hardware cycle time tuning. Mr. Doettling studied electrical engineering at the University of Stuttgart, Germany, and received a master's degree in 1978. The same year, he started work at SEL Stuttgart, Germany, in digital telephone switching system design. In 1981, he joined the IBM Germany Development Laboratory in Boeblingen. Since then, Mr. Doettling has worked as a key designer and as a team and project leader on several generations of IBM servers, CMOS microprocessors, and I/O chip designs.

Richard F. Rizzolo IBM Systems and Technology Group, 2455 South Road, Poughkeepsie, New York 12601 (rizzolous.ibm.com). Mr. Rizzolo is a Senior Technical Staff Member and served as test team leader for several System z projects, most recently for the System z9. He also has primary responsibility for the sort and characterization methodology for MCM chips designed in Poughkeepsie, New York. He received his B.S. degree in physics from Rensselaer Polytechnic Institute in 1977 and his M.E. degree in electrical engineering from Rensselaer in 1980. Since joining IBM in 1978, Mr. Rizzolo has worked on bipolar and CMOS projects in the areas of design for testability, high-frequency design and timing analysis, diagnostics, and circuit design. He holds ten patents and has co-authored a number of papers in the field of testability and diagnostics.

Christopher J. Berry IBM Systems and Technology Group, 2455 South Road, Poughkeepsie, New York 12601 (cberryus.ibm.com). Mr. Berry is an Advisory Engineer working in the IBM Hardware Development Laboratory. In 1999 he joined IBM at the Poughkeepsie site working for the System z Microprocessor Design group. He became a chip integrator at the beginning of 2000 and led the physical design and integration for the System z9 processor subsystem chipset. Mr. Berry received a B.S.E.E. degree from Rensselaer Polytechnic Institute in 1999.

Sean M. Carey IBM Systems and Technology Group, 2455 South Road, Poughkeepsie, New York 12601 (smcareyus.ibm.com). Mr. Carey is a Senior Technical Staff Member with the System/390* Hardware Development Laboratory. Since joining IBM Poughkeepsie in 1988, he has worked in the hardware development area on several System/390 projects, with emphasis on timing methodology support and development. Mr. Carey received a B.S.E.E. degree from Clarkson University in 1988 and an M.S.E.E. degree from Syracuse University.

Christopher M. Carney IBM Systems and Technology Group, 2455 South Road, Poughkeepsie, New York 12601 (carneyccus.ibm.com). Mr. Carney joined IBM in 2001 and is a Staff Engineer in the System/390 Hardware Development Laboratory. He began his career as a logic designer working on the System z990 and is currently the L2 nest timing coordinator for the next-generation mainframe. Mr. Carney received a B.S.E.E. degree from Pennsylvania State University in 1996 and an M.S.E.E. degree from Binghamton University in 2001.

Joachim Keinert IBM Systems and Technology Group, IBM Deutschland Entwicklung GmbH, Schoenaicherstrasse 220, 71032 Boeblingen, Germany (keinertde.ibm.com). Mr. Keinert received his M.S. degree in electrical engineering from the Technical University of Stuttgart, Germany, in 1980. He joined IBM in 1979 to work on bipolar circuit design. In 1982, he began work on CMOS circuit tool development and chip-design methodologies. Since then, he has been involved in the development of design tools for all IBM CMOS mainframe processors. His work also covers innovative technologies such as FinFETs, and he holds patents in various areas. Currently, Mr. Keinert is a focal point for circuit design tools for future IBM eServer* processors.

Peter Loeffler IBM Systems and Technology Group, IBM Deutschland Entwicklung GmbH, Schoenaicherstrasse 220, 71032 Boeblingen, Germany (ploeffde.ibm.com). Mr. Loeffler joined IBM in 1994 and worked on hardware compression logic design for CMOS microprocessors for System/390 mainframes. In 1998, he moved to the IBM facility at Poughkeepsie, New York, on a two-year assignment, joining the I- and D-cache design team to work on high-frequency design as a unit timing coordinator for the G4 System z processor. Returning to Boeblingen in 2000, he joined the System z990 translator team and was responsible for unit timing coordination. For the System z9 microprocessor chip, he was the chip/core timing leader. Mr. Loeffler received his B.S. degree in communications engineering from the University of Applied Sciences, Esslingen, Germany, in 1994.

Walter Nop IBM Systems and Technology Group, 2455 South Road, Poughkeepsie, New York 12601 (wnopus.ibm.com). Mr. Nop is an Advisory Engineer in the IBM Hardware Development Laboratory. In 1988, he joined the IBM facility in Essex Junction, Vermont. He joined the System z microprocessor design group in Poughkeepsie in 1999 as a unit integrator and was integration leader for the System z9 microprocessor. Mr. Nop received a B.S.E.E. degree from Rochester Institute of Technology in 1999.

Daniel E. Skooglund IBM Systems and Technology Group, 2455 South Road, Poughkeepsie, New York 12601 (skooglunus.ibm.com). Mr. Skooglund is a Senior Engineering Manager of a processor design department in the IBM Systems and Technology Group. He received a B.S.E.E. degree from Pennsylvania State University in 1982 and an M.S.E.E. degree from Syracuse University in 1988. Mr. Skooglund joined IBM in 1982 at the East Fishkill facility, where he developed and managed advanced VLSI logic and memory test systems. In 1993, he joined an applications support group in East Fishkill, where he worked with the IBM Storage Group on the development of SCSI hard disk controllers. In 1999, he joined the System z processor development group in Poughkeepsie as a design manager responsible for back-end design methodology, chip integration, and physical design for high-frequency custom microprocessors. Mr. Skooglund was the processor subsystem design manager for the System z9; he is currently working on the next generation of eServer processors.

Vern A. Victoria IBM Systems and Technology Group, 2455 South Road, Poughkeepsie, New York 12601 (vernvus.ibm.com). Mr. Victoria is a Senior Engineer in the Systems and Technology Group server development area. He received a B.S. degree in mathematics and physics from Kent State University in 1981. He received his M.S. degree in mathematics from Carnegie Mellon University in 1983, joining the Poughkeepsie server development group that same year as a programmer working on boolean equivalence checking and timing analysis. He later worked as an engineer performing timing analysis and optimization on emulator processor chips. He worked on early SOI evaluation chips and SiGe chips. He is currently the team leader for timing of the memory controller, system controller, and L2 cache. Mr. Victoria has received an IBM Outstanding Technical Achievement Award for S/390* G5 library development.

Alan P. Wagstaff IBM Systems and Technology Group, 2455 South Road, Poughkeepsie, New York 12601 (alanpwagus.ibm.com). Mr. Wagstaff is a Staff Engineer in the Systems and Technology Group. He joined IBM in 2002 at the Poughkeepsie site, working on the System z9 product line as an integrator. Mr. Wagstaff received a B.S.E.E. degree in 2001 and an M.S.E.E. degree in 2002, both from Carnegie Mellon University.

Patrick M. Williams IBM Systems and Technology Group, 2070 Route 52, Hopewell Junction, New York 12533 (patricwus.ibm.com). Mr. Williams is the manager of the Electronic Design Automation Circuits Department. In 1984, he joined IBM at the East Fishkill facility, where he developed VLSI high-speed memory test systems. In 1992, he joined the advanced CMOS microprocessor team in Poughkeepsie. He was initially part of the SRAM development team, and in 1994 joined the CAD development team in support of the System z line of microprocessors. He has held various lead roles in both circuit and integration CAD methodology and development. Mr. Williams has been involved in many aspects of CAD development in support of high-speed microprocessors, including timing analysis, noise analysis, power analysis, IR drop analysis, electromigration analysis, device and parasitic extraction, chip integration, circuit optimization, electrical circuit checking, and layout automation. He received a B.S.E.E. degree from Pennsylvania State University in 1984. Mr. Williams has several U.S. patents and publications.

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