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IBM Journal of Research and Development
IBM System z9   Volume 51, Number 1/2, 2007
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Decimal floating-point in z9: An implementation and testing perspective - References

 by A. Y. Duale,
M. H. Decker,
H.-G. Zipperer,
M. Aharoni,
and T. J. Bohizic
References

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  2. M. F. Cowlishaw, “Decimal Floating-Point: Algorism for Computers,” Proceedings of the 16th IEEE Symposium on Computer Arithmetic, Santiago de Compostela, Spain, June 2003, pp. 104–111; see http://www2.hursley.ibm.com/decimal/IEEE-cowlishaw-arith16.pdf.
  3. “Draft Standard for Floating-Point Arithmetic,” IEEE, Draft 1.2.5, October 4, 2006; see http://754r.ucbtest.org/drafts/754r.html.
  4. L. C. Heller and M. S. Farrell, “Millicode in an IBM zSeries* Processor,” IBM J. Res. & Dev. 48, No. 3/4, 425–434 (2004).
  5. M. Cowlishaw, “Densely Packed Decimal Encoding,” IEEE Proc. Computers & Digital Tech. 149, No. 3, 102–104 (2002).
  6. IBM Corporation, z/Architecture Principles of Operation (SA22-7832); see http://publibz.boulder.ibm.com/epubs/pdf/a2278324.pdf.
  7. M. A. Erle, M. J. Schulte, and J. G. Linebarger, “Potential Speedup with Decimal Floating-Point Hardware,” Proceedings of the 36th Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, CA, November 2002, pp. 1073–1077.
  8. B. Wile, M. P. Mullen, C. Hanson, D. G. Bair, K. M. Lasko, P. J. Duffy, E. J. Kaminski, Jr., et al., “Functional Verification of the CMOS S/390 Parallel Enterprise Server* G4 System,” IBM J. Res. & Dev. 41, No. 4/5, 549–566 (1997).
  9. Floating-Point Test Generator—FPgen, IBM Corporation; see http://www.haifa.ibm.com/projects/verification/fpgen.
  10. A. Chandra, V. Iyengar, D. Jameson, R. Jawalekar, I. Nair, B. Rosen, M. Mullen, et al., “AVPGEN—A Test Generator for Architecture Verification Source,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 3, No. 2, 188–200 (1995).
  11. A. Duale, T. Bohizic, M. Decker, D. Wittig, and G. Darling, “Generation of Pseudo-Random Test Cases,” Proceedings of the 6th World Multiconference on Systemics, Cybernetics and Informatics (SCI), Orlando, FL, 2002, pp. 338–341.
  12. A. Y. Duale, T. J. Bohizic, and D. W. Wittig, “Pseudo-Random System Testing: Coverage Estimation and Enhancement,” Proceedings of the International Conference on Software Engineering Research and Practice, Las Vegas, NV, June 2005, pp. 283–289.
  13. M. Bailey, T. E. Moyers, and S. Ntafos, “An Application of Random Testing,” Proceedings of the IEEE Military Communications Conference, November 1995, pp. 1098–1102.
  14. B. Beizer, Software Testing Techniques, Van Nostrand Reinhold, New York, 1990.
  15. T. Y. Chen and Y. T. Yu, “On the Relationship Between Partition Testing and Random Testing,” IEEE Trans. Software Eng. 20, No. 12, 977–980 (1994).
  16. W. H. Debany, C. R. P. Hatmann, K. G. Mehrotra, and P. K. Varshaney, “Comparison of Random Test Vector Generation Strategies,” Proceedings of the IEEE International Conference on Computer-Aided Design, Santa Clara, CA, November 1991, pp. 244–247.
  17. L. Fournier, Y. Arbetman, and M. Levinger, “Functional Verification Methodology for Microprocessors Using the Genesys Test-Program Generator,” Proceedings of the Conference on Design Automation and Test, Munich, Germany, 1999, pp. 434–441.
  18. M. Karam and G. Saucier, “Functional Versus Random Test Generation for Controllers and Finite State Machines,” Proceedings of Euro ASIC, Paris, France, 1992, pp. 207–212.
  19. S. C. Ntafos, “On Comparisons of Random, Partition, and Proportional Partition Testing,” IEEE Trans. Software Eng. 27, No. 10, 949–960 (2001).
  20. M. Cowlishaw, “The decNumber C Library,” Version 3.37, IBM UK Laboratories, November 22, 2006; see http://www2.hursley.ibm.com/decimal/decnumber.pdf.
  21. D. F. Ackerman, M. H. Decker, J. J. Gosselin, K. M. Lasko, M. P. Mullen, R. E. Rosa, E. V. Valera, and B. Wile, “Simulation of IBM Enterprise System/9000* Models 820 and 900,” IBM J. Res. & Dev. 36, No. 4, 751–764 (1992).
  22. N. L. Schryer, “A Test of a Computer's Floating-Point Arithmetic Unit,” Computer Science Technical Report 89, AT&T Bell Laboratories, 1981.
  23. M. Parks, “Number-Theoretic Test Generation for Directed Rounding,” IEEE Trans. Computers 49, No. 7, 651–658 (2000).
  24. M. Aharoni, S. Asaf, L. Fournier, A. Koifman, and R. Nagel, “FPgen—A Test Generation Framework for Datapath Floating-Point Verification,” Proceedings of the Eighth IEEE International High-Level Design Validation and Test Workshop 2003 (HLDVT03), November 2003, pp. 17–22.

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