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IBM Journal of Research and Development
IBM System z9   Volume 51, Number 1/2, 2007
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High-speed source-synchronous interface for the IBM System z9 processor - References

 by D. M. Berger,
J. Y. Chen,
F. D. Ferraiolo,
J. A. Magee,
and G. A. Van Huben
References

  1. HyperTransport Consortium, “Welcome to the HyperTransport Consortium”; see http://www.hypertransport.org.
  2. E. Cordero, F. Ferriaolo, M. Floyd, K. Grower, and B. McCredie, “A Synchronous Wave-Pipeline Interface for POWER4,” presented at the IEEE Computer Society HOT CHIPS Workshop, Stanford University, California, 1999.
  3. T.-M. Winkel, W. D. Becker, H. Harrer, H. Pross, D. Kaller, B. Garben, B. J. Chamberlin, and S. A. Kuppinger, “First- and Second-Level Packaging of the z990 Processor Cage,” IBM J. Res. & Dev. 48, No. 3/4, 379–394 (2004).
  4. H. Harrer, D. M. Dreps, T.-M. Winkel, W. Scholz, B. G. Truong, A. Huber, T. Zhou, K. L. Christian, and G. F. Goth, “High-Speed Interconnect and Packaging Design of the IBM System z9 Processor Cage,” IBM J. Res. & Dev. 51, No. 1/2, 37–52 (2007, this issue).


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