Three-dimensional integrated circuits

The development of IC technology is driven by the need to increase both performance and functionality while reducing power and cost. This goal has been achieved by the use of two solutions: 1) scaling devices and associated interconnecting wire [1] through the implementation of new materials and processing innovations, and 2) introducing architecture enhancements [2] to reconfigure routing, hierarchy, and placement of critical circuit building blocks. Challenges associated with process scaling and architectural scaling are discussed in the following paragraphs.

• Front-end-of-line (FEOL) scaling: As accelerated gate-length scaling has pushed the gate-dielectric and junction technology to its physical limits, continued conventional bulk-Si CMOS device scaling of the oxide thickness, junction depth, and depletion width [3] has become quite difficult, possibly necessitating the replacement of bulk MOSFETs with novel CMOS device structures. Silicon-on-insulator (SOI) technology, which offers higher performance because of junction capacitance reduction and lack of body effects, has been developed [4]. Further, scaling of SOI thickness reduces short-channel effect and eliminates most of the leakage paths [5], but it rapidly degrades mobility, thereby limiting the extent of SOI scaling [6]. Strained Si channels offering mobility enhancement have been demonstrated [7], but future structures which combine the benefit of SOI and strained silicon technology may have to be constructed by using device geometry and technology developed for double-gate FETs [8] and FinFETs [9]. A key challenge for these novel integration and device options is the increasing difficulty in their fabrication and the incompatibility of various designs with planar structures [10].

• Back-end-of-line (BEOL) scaling: CMOS scaling trends result in a design in which billions of transistors are interconnected by tens of kilometers of wires packed into an area of square centimeters [11]. Wires deliver power to each transistor and provide a low-skew synchronizing clock. However, increasing wiring complexity and challenges in improving wire delay to keep up with intrinsic gate delay are key issues for BEOL technology [12]. Although many new materials and processes have been introduced to meet metal conductivity and dielectric permittivity requirements, it is expected that interconnect metallization of long wires with resulting RC delay, low yield, and high cost of fabrication will limit the performance of ICs beyond the 45-nm-technology node [13].

• Architecture: The conventional planar IC has limited floorplanning choices, and these in turn limit system architecture performance improvements. This leads to issues related to the interconnect loading in the network of long wires and the need for signal repeaters used for clock distribution. However, repeaters are responsible for a significant fraction of the total power consumption on a chip. Also, existing two-dimensional (2D) IC designs may not be suitable for the integration of disparate signals (digital, analog, or rf) or technologies (SOI, SiGe, heterojunction bipolar transistors or HBTs, GaAs, etc.) [14]. In addition, because of IC scaling trends, traditional computer-aided-design (CAD) practices and tools have required an increased number of design cycles, raising time to market and cost per chip function [15]. Therefore, a solution is required that both alleviates the interconnect bottleneck and provides new avenues for the advanced device and architectural innovation.

One of several promising solutions being explored is the 3D integration and packaging technology (also known as vertical integration), in which multiple layers of active devices are stacked with vertical interconnections between the layers (Figure 1) to form 3D integrated circuits (ICs) [16]. Later sections present a detailed description of this technology. Even in the absence of continued device scaling, 3D ICs provide potential performance advances, since each transistor in a 3D IC can access a greater number of nearest neighbors, and each circuit functional block has higher bandwidth. Other benefits of 3D ICs include improved packing density, noise immunity, improved total power due to reduced wire length/lower capacitance, superior performance, and the ability to implement added functionality. These features are described in more detail in the following sections.

Figure 1

Initial analyses of investigated 3D wire-length reduction [11] showed that 3D integration indeed provides a smaller wire-length distribution, with the largest effect associated with the longest paths. These shorter wires will decrease the average load capacitance and resistance and decrease the number of repeaters needed for long wires. Since interconnect wires with their supporting repeaters consume a significant portion of total active power, the reduced average interconnect length in 3D IC, compared with that of 2D counterparts, will improve the wire efficiency (~15%) and significantly reduce total active power by more than 10% [17].

The shorter interconnects and consequent reduction of load capacitance in 3D ICs will reduce the noise due to simultaneous switching events. The shorter wires will also have lower wire-to-wire capacitance, resulting in less noise coupling between signal lines. The shorter global wires with reduced numbers of repeaters should also have less noise and less jitter, providing better signal integrity.

Because MOSFET fan-out is limited to a fixed amount of capacitive gain per cycle, the increasing intrinsic gate load is significantly constrained by extrinsic load capacitance (wires). Since 3D IC provides a lower wiring load, it makes it possible to drive a greater number of logic gates (fan-out) [18].

In three dimensions, active devices can be stacked and the size of a chip footprint can be reduced. This added dimension to the conventional two-dimensional device layout improves the transistor packing density, since circuit components can be stacked on top of each other, as in Figure 2, where an n-FET is placed over a p-FET. When the total layout area (the sum of the device area and the metal routing area) is compared for 2D and 3D standard cells with different inverter designs, a 30% areal benefit for the 3D cells can be achieved [18]. The ability to stack circuit elements, thus shrinking the footprint and potentially reducing the volume and/or weight of a chip, is of great interest for wireless, portable electronics, and military applications.

Figure 2

Higher-density and hence higher-speed SRAM circuits can also be created. For example, the pull-up p-MOS devices could be stacked over the n-MOS in a 3D approach to save device area. However, since metal routing occupies a large portion of the total layout area, the total cell area reduction will depend strongly on the chip architecture and the metal routing design. Successful stacked CMOS SRAM cell technology has been reported [19], but its extendibility is limited by extremely tight alignment tolerance requirements for interlayer contacts.

3D technology enables the memory arrays to be placed above or under logic circuitry, resulting in an increased bandwidth and thus a significant performance gain in communication between memory and microprocessor. In particular, as the amount of on-chip memory increases (i.e., the majority of the chip will soon be occupied by memory), the latency of the path from logic to memory becomes a limiting factor in the logic-memory system. The ability to stack logic and memory has been demonstrated [20].

In addition, one can determine maximum system performance as a function of the number of device layers. Maximum performance depends on power dissipation constraints. In the presence of power constraints, there are global technology scaling optima that yield maximum computation (for example, if devices are scaled too far, leakage consumes too much of the power). Simple models of device and system dependencies have been developed, and optimizations have been performed. These layering models ignore the impact of blockage due to signals passing through a device layer. As depicted in Figure 3, the results show significant potential advantage for 3D integration, with performance increasing roughly as the square root of the number of circuit layers that are stacked. For these data points, device characteristics (such as V_dd, V_T, t_ox, gate length, mean FET width, wire half-pitch, and repeater spacing) have all been optimized for maximum performance [21], where performance is calculated as Performance = total number of logic switching events per second in a processor core.

Figure 3

3D integration will allow the incorporation of new elements that are currently prohibited by conventional planar technology; it will enable the implementation of related design flexibility, including new system architectures. Its primary application is the combination of dissimilar technologies (memory, logic with extension to rf, analog, optical, and microelectromechanical systems) to create hybrid circuits [22].

3D IC fabrication technology can be accomplished by the implementation of diverse processing sequences. The simplest way to distinguish among various methods is by differentiating between chip-level and wafer-level processing during the layering of key circuit components. Then the process can be further differentiated by determining whether the layer stacking was done using a face-to-face or face-to-back approach. A detailed description of some of the most promising 3D assembly methods is presented in next few subsections.

3D stacking technology was established for packaging [17] and focused mainly on chip-stacking methods. Today many 3D packaging systems are manufactured, but high-density memory modules are a key application [23]. Typically a 3D package stacks bare dies or multichip modules (MCMs), securing the full chips by using epoxy or glues and creating electrical connections by wire-bonding techniques. Novel 3D packages utilize peripheral interconnections that are several millimeters long [24], but higher interconnect density with shorter links (hundreds of microns) between stacked layers has also been demonstrated by incorporating conducting vertical through-hole vias across the chip [23]. 3D packaging has relaxed interconnect pattern geometry and alignment accuracy requirements when compared with 3D ICs. Hence, a key process technology element being optimized for 3D IC is a methodology for higher-density, smaller-dimension interlayer connections. Chip-to-chip and chip-to-wafer methods have been utilized to accomplish this goal and are discussed in sections that follow.

A wafer-level stacking of 3D ICs potentially enables a more cost-effective solution than the chip-stacking techniques. 3D IC wafer-scale technology (currently a 200-mm and soon a 300-mm option) has the advantage of potentially offering increased design flexibility, since many key processing steps have not been developed at the die level. There are two primary schemes for wafer-scale integration of 3D circuits: “bottom-up” and “top-down” fabrication.

Bottom-up wafer-scale fabrication
In the bottom-up approach, the layering process is sequential and may not require wafer stacking. More specifically, the bottom-most layer is first created using standard CMOS technology, followed by the formation of a second Si layer, and device fabrication on the second layer. Additional layers can be added on the top in a similar fashion. The subsequent Si layers are fabricated without additional wafer stacking using solid-phase crystallization [20], the implementation of seeding agents such as germanium or nickel [25], lateral overgrowth [26], or the implementation of wafer-bonding techniques [27] to provide a new Si substrate. The latter methods provide single-crystal silicon and result in improved device quality in comparison with the first method [28]. However, thermal budget constraints, facilitated to maintain good performance in the underlying IC layers, are a concern for all of these technologies.

Top-down wafer-scale fabrication
In the top-down method, multiple 2D IC circuits can be fabricated in parallel and then “assembled” to form 3D IC [16]. Such an approach enables the performance optimization of each layer and its functional verification prior to stacking, and results in acceptable yield and lower manufacturing cost. It is particularly attractive for applications in which layers of disparate technologies are closely stacked. Key process challenges of the top-down 3D IC technology include high-quality, low-temperature bonding (<400°C), as back-end materials (metals and low-k) may already be a part of the structure, tight alignment tolerances, the integrity of contacts between device layers, and high process reliability [16].

As shown in Figure 4, 3D IC structures may also be characterized according to the parts of the circuit design that are layered. More specifically, the 3D integration can be application-specific, and conceptually it can be partitioned as stacking layers of devices, circuits, macros, circuit functional units, or chips. As depicted in Figure 4, depending on 3D application or partition level, a specific input/output (I/O) or interlayer via density is achievable.

Figure 4

Further, depending on the position of the top of the second layer with respect to the top of the first layer after stacking, the process can be described as “face-to-face” if the two tops are facing each other, or “face-to-back” if they are not. The most promising methods for creating 3D ICs using face-to-face and face-to-back options are depicted in Figure 5, and their assembly technology features are listed in Table 1. In general, these options can be used to build chip-to-chip, wafer-to-wafer, and chip-to-wafer 3D ICs, but a specific process flow may be easier for a particular chip- or wafer-level technology, and it is often driven by a specific application.

Figure 5

Figure 5(a) shows a structure in which the distance between device layers is minimized by removing the entire Si substrate between the layers. Bonding between the device layers is achieved through blanket dielectric fusion bonding or the use of an adhesive interlayer, after which interlayer electrical connections are formed [29]. Figure 5(b) shows the face-to-face bonding option, which is effective for creating high-density Cu–Cu bonded links between layers but requires deep vias for bringing signals out to the package [30]. The structure in Figure 5(c) typically has the largest interlayer via dimensions and the lowest via density, along with the most relaxed alignment tolerances [31]. The choice of structure and fabrication method depends on the specific goal and application of the 3D IC technology.

The IBM 3D assembled structure [Table 1, column (a)] is described as having the shortest distance between stacked device layers, the highest interconnection density, and extremely aggressive wafer-to-wafer alignment requirements. By using IBM methodology, unique n-FET and p-FET layers can be stacked to derive full benefit from the 3D IC process. The process flow to fabricate such structures is depicted in Figure 6. With stringent design requirements, the key process optimization focused on development of state-of-the-art interdevice layer connections.

Figure 6

Independent of the final 3D IC structure, the assembly method always involves the integration of four key technology areas: thinning of the wafers, interdevice-layer alignment, bonding, and interlayer contact patterning. An additional challenge in achieving high-density I/O signal through the stack layers arises from thermal mismatch between the bonded layers, affecting alignment tolerance. Also, thermal dissipation of high-performance CMOS devices is already a concern in 2D ICs; for 3D circuits, heat spreading and self heating become critical issues. All of these 3D IC integration challenges require new material and process innovations [29]; the following sections of this paper discuss related IBM solutions.

Techniques based on mechanical grinding and polishing and plasma or wet etching have been demonstrated to reliably thin 200-mm silicon wafers to ~20-μm thicknesses. To facilitate the removal of bulk Si, the prominent feature of most IBM 3D IC work is the use of SOI and glass substrates. The buried oxide layer (BOX) serves as an etch stop for substrate thinning, enabling the use of high-performance state-of-the-art IC technology. More specifically, the BOX in SOI wafers provides a selective etch stop for the uniform removal of the Si substrate; combined with the use of a glass substrate, it enables improved alignment capabilities (Figure 6). Both features greatly simplify the layer-transfer process, providing a means of obtaining the shortest distance between devices. The final “decal” structure on a glass carrier has all of the bulk Si removed; only the device layer with its metallization levels remains, making the stack transparent and hence enabling the “through-wafer” alignment process.

Standard alignment methodology allows both front-side (through-wafer) and back-side alignment strategies. A primary challenge for future high-density 3D ICs is the requirement for high (submicron) alignment tolerances to facilitate higher-level circuit designs. As tested using current available commercial alignment tools, 3 sigma value (3σ) of ~1.0 μm is the best alignment accuracy achieved at present using the through-wafer alignment strategy (glass substrate); it is ~1.0 μm lower than the best results from nontransparent alignment methods (back-side alignment strategies). In addition, for multiple stacked fully thinned IC device layers, signal degradation caused by alignment through glass is not expected, and good alignment can easily be achieved. If a nontransparent carrier is used, the wavelength-dependent signal attenuation through Si may degrade alignment accuracy (especially for layers in which remaining Si is thicker than 40 μm) [32]. Therefore, the tradeoff between resolution and transparency in Si poses a real challenge for nontransparent wafers which is circumvented by the use of a glass for which the CTE is matched to that of silicon.

Alignment error due to the difference in the CTE of the two layers was minimized in the SOI-based face-to-back process by utilizing oxide-fusion bonding at room temperature. When compared with other bonding methods, oxide-fusion bonding shows clear superiority (Table 2) because it allows wafer to be tacked in place at room temperature during alignment. We have shown that increased temperature during the post-bonding anneal strengthens the bond but does not change the alignment accuracy [32]. In comparison, since Cu bonding occurs at higher temperatures, extremely good temperature control must be maintained. Accuracy using bonding with adhesive layers may be degraded, as adhesives may become viscous during the bonding process (temperature and compression cycle), thus causing alignment patterns to shift. It is important to notice that the placement error of state-of-the-art lithography tools is <0.02 μm and as such does not limit alignment precision [33].

Large alignment errors may be induced by bowing of the wafers. Every processing step changes the bow of a wafer, sometimes by hundreds of microns [32]. To achieve optimal alignment results, the bow should be less than 20 μm for 200-mm wafers during alignment. To maintain this bow target, compensation methods, such as the deposition of counter-pre-stressed films, have been implemented prior to the bonding step. Similarly, surface smoothness and local planarity are critical for high-accuracy alignments, as they affect the ability of the optics of an alignment tool to focus on alignment mark structures.

For all types of bonding methods, the quality of the bonded interface depends strongly on surface roughness and cleanliness. In particular, a fusion bonding requires atomically smooth surfaces. The combination of chemical–mechanical polishing (CMP) and wet chemical surface treatment is often used prior to bonding to ensure clean and reactive bonding surfaces. Cleaning procedures and a post-deposition annealing sequence control bond strength in that they reduce the formation of voids at the bonding interface and must be optimized for every set of bonded materials. More specifically for the oxide-fusion bonding process, reduction of the bulk concentration of –OH groups in oxide (post-deposition) before bonding enhances the ability of the oxide to absorb byproducts released during the bonding anneal and is critical in obtaining defect-free bonded interfaces [34]. Figure 7 shows a cross-sectional TEM image of two SOI CMOS device layers bonded by oxide fusion.

Figure 7

Since surface root mean square (RMS) roughness requirements for fusion-bonded surfaces are very stringent (<1.0 nm) and not easily achieved, many researchers turn to metal-to-metal bonding options because their RMS roughness specifications can be higher (<20 nm). However, the drawback of the metal-to-metal low-temperature bonding process is that high pattern density is required to provide high bond strength and interface stability during further processing steps. Bonding using polymeric or dielectric glue layers has the least stringent surface planarity requirements, but the use of viscous glue may lead to shifts of these layers during bonding, thereby limiting alignment tolerance (Table 2). Temperatures for all of these bonding approaches must be compatible with the thermal constraints of each functional layer, typically ~450°C for post-CMOS FEOL processes. The quality of the bonded interface (bond strength, void content, and cleanliness) is critical in ensuring high yields in the fabrication of interlevel vias, and may be a key factor in bonded device reliability characteristics.

For all three structures depicted in Figure 5, the 3D IC technology requires the formation of high-aspect-ratio (AR) vias. The patterning and metallization process for the creation of such vias (e.g., plasma etch, metal fill, and CMP) must be compatible with other BEOL process strategies. All metallization techniques place specific limitations on the maximum aspect ratio of vias, and may thus lead to design limitations with respect to the layout of active and passive devices on each layer. As stated earlier, the BOX layer in a SOI substrate is used to control the transferred device layer thickness to very tight tolerances. This in turn minimizes the effective aspect ratio of the interwafer via by enabling vertical stacking of the layers spaced only a few microns apart. To utilize the full potential of 3D IC, vias of submicron diameter dimensions are required to be compatible with state-of-the-art FEOL technology. Hence, the performance and eventual viability of the 3D ICs built by stacking high-performance CMOS devices depends critically on bonding alignment tolerances and on the structural and electrical integrity of the submicron high-aspect-ratio vias connecting device layers.

Figure 8 shows our capability to fabricate small (submicron) interconnecting 3D IC copper-filled vias with high aspect ratios (6:1 < AR < 11:1) using a single-damascene process [34]. The via profile, metal liner, and Cu plating processes were modified only slightly from a standard back-end-of-line via formation sequence to achieve proper fill of these high-aspect-ratio structures. The smallest vias, with a bottom diameter of ~0.14 μm, height >1.6 μm, and sidewall angle of approximately 86 degrees, can be formed on a 0.4-μm pitch, equivalent to an extremely high via density of >10⁸ vias per cm².

Figure 8

Vias with bottom critical dimensions (CDs) of ~0.14 μm × 0.14 μm correspond to a 0.13-μm CMOS BEOL technology, but owing to the higher aspect ratio of the interlevel vias in 3D ICs, their resistance is expected to be two to three times higher than that of a typical back-end via. Measurements of resistance per link of 3D via chains connecting the first metal level of top and bottom wafers indicate resistance values of ~2–4 Ω per link and good yield for via chains with 100–10,000 vias [32]. This confirms a successful metallization process through the bonded interface. Further process optimization is required to achieve acceptable yields for the longer chain lengths. One should notice, however, that vias with such high density would rarely be used because of the space that would be taken up by active circuitry on the upper device layer and because of alignment challenges. Nevertheless, this process illustrates a technique for building ultrahigh-density, low-parasitic links between layers using materials and processes compatible with pre-fabricated circuitry. The alignment accuracy required to reliably interconnect the various device circuits fabricated ranges from 0.5 to 2.5 μm and has been successfully achieved.

Device temperature increase is already a major concern in 2D SOI technology. Because of the poor heat conductivity of the BOX layer, temperature increases of 80–120°C/mW/μm of width in transistors have been reported [35]. In addition, a rise in temperature causes device performance variation and can be very critical for matching in analog circuits. Also, the performance of the clock buffer is affected by device temperature increases. Calculations show that for SOI and bulk devices, every 10°C increase in junction temperature degrades clock buffer performance by 1.2% and 1.32%, respectively. Various tests, including pulsed I–V, body-contact diode, polySi resistance, and subthreshold slope methods, have been used to measure temperature in 2D SOI transistors¹ [35–37] and may be utilized to test 3D ICs. The reduced surface-area-to-volume ratio of 3D structures will inevitably lead to increases in power density and may potentially affect the intrinsic heating of high-performance chips. Therefore, for some applications the use of heat-dissipating structures to minimize thermal gradients and local heating may be required, but it could affect the interlevel interconnect layout and the design of the 3D chip [38]. To address all of these 3D IC critical issues, a reliable set of verification test structures (described below) is required.

Figure 9 shows an example of a 3D via-chain structure for resistance measurements. Via chains go back and forth between the first metal levels of the top and bottom wafers. All test pads are at the top wafer. There are two pads for each end of a via chain to enable four-point resistance measurement. These simple test structures can show whether low parasitic connections have been made between bonded layers using materials and processes compatible with prefabricated circuitry. As indicated in Figure 8, a single-damascene process can be used to fabricate such submicron, Cu-filled vias, reliably connecting top and bottom wafers.

Figure 9

Bond strength measurement is a good first-pass method of evaluating the quality of the bonded interface, but it is not sufficient from a device reliability point of view. For example, TEM-based measurement of the oxide-fusion-bonded interface in Figure 10 exhibits a 2% aerial void density, but it yields a high bond strength of ~2.2 J/m² (wedge test depicted in the Figure 10 insert). To better evaluate the oxide-fusion-bonded interface, IBM utilizes via-chain test structures with submicron vias, which are sensitive to leakage induced by a poor interface. Comparisons such as the one shown in Figure 11 measure the resistance of interlevel via chains of various lengths, patterned-through oxide with and without the bonded interface, indicating that the resistance of the interlevel vias, patterned through the bonded interface, is within the expected value (<4 Ω per link) for Cu vias having this aspect ratio.

Figure 10 Figure 11

We have developed several techniques to optically and electrically align 3D layers and at the same time be able to measure the resultant overlay error. Two of the optical alignment test structures are shown in Figures 12(a) and 12(b). These structures can be used for automated or manual bonding alignment and for measurement of the resultant overlay [39]. Figure 12(a) shows an image of a standard box-in-box structure. For 3D IC applications, however, here the outer box comes from the upper device layer and the inner box from the lower device layer. By design, the center of the smaller box should be 13.0 μm away from the edge of the bigger box. Therefore, simply by measuring the difference in distance between the two boxes, the alignment accuracy in both the x and y directions can be determined.

Figure 12

Another example of an optical alignment test structure, a Vernier-type structure, is shown in Figure 12(b), where alignment between metal levels in the bottom and top wafers is measured. In this design, Vernier patterns are placed in both the x and y directions, creating a structure for resolving misalignment at 0.18-μm granularity. We have shown nearly perfect <0.18-μm alignment in both the x and y directions at one particular spot on the wafer [32]. This is a significantly better result than the best reported alignment precision for a 200-mm-diameter wafer to date. One must consider, however, that alignment across the whole wafer degraded, and by optical measurements only 65% of the area is within the required <2.5-μm alignment precision.

In addition to optical test structures, we have also designed a resistor chain structure to electrically measure bonding alignment for 3D stacked circuits [39]. The chain is fabricated in the bottom wafer, having polySi resistors along the metal chain. Using an interlevel via, the center terminal from the bottom chain taps into a metal leg in the top wafer track, creating a voltage divider circuit. Such a measurement across the wafer generates electrical maps of layer-to-layer registration. If there is a bonding misalignment, the interlayer via will miss the targeted metal leg in the bottom wafer and land on a different one. In this design, the mismatch in voltage reading depends on the misalignment, sizes of metal chain pitch, and interwafer via dimension. The same approach can also be used for patterns without added polySi resistance along the metal chain (metal chain method). Figure 13 shows typical test results of alignment measurements for testing with via sizes of 140 nm, 180 nm, and 250 nm bottom critical dimension. The results are very promising, since all of the chains tested across the wafer fit within the required (0.5–2.5 μm) alignment tolerance, and most of them are <1 μm. Many other test structures using via-chain elements can be designed to evaluate alignment.

Figure 13

Thermal issues in 3D ICs become severe with increased power density and thermal resistance from stacking multiple layers. To evaluate the thermal aspects of the 3D vs. 2D ICs, subthreshold slope and polySi resistance methods are used in 3D macros for self- and spread-heating measurements. Tests include quantifying self-heating in a single transistor and spread-heating through shared Si islands in two-finger transistors (Figure 14). While most studies focus on device self-heating, in our work we also consider spread-heating, defined as the temperature rise of a transistor due to the power dissipation of its neighbors in horizontal and vertical directions. Figure 14(a) shows a 28-finger n-FET with its center finger connected for four-point resistance measurement. The rest of the fingers are connected to drive the transistor with one gate terminal. The transistor is laid out in 3D for self-heating measurements in the top and/or bottom wafer. This cell is connected such that the temperature rise can be measured in both ac and dc operating modes. These test structures have been fabricated successfully, but the final analysis has not yet been completed.

Figure 14

ANSYS** simulation work suggests that the temperature drops very rapidly in shallow-trench isolation (STI) around an isolated electrically ON transistor: 80% within 0.5 μm in 0.13-μm SOI CMOS technology. Therefore, five transistors are separated 0.2 μm, 0.5 μm, 1 μm, and 2.98 μm from one another on each wafer in a two-wafer 3D chip, as shown in Figure 14(b), with the goal of characterizing spread-heating effects through STI and 3D BOX with interconnect layer. Transistors from top and bottom wafers are connected in such a way that each transistor has its own source terminal and all transistors share a common shorted drain and gate terminal. While the experiments are being conducted, the common drain and gate terminal must be tied to V_dd. Then, applying V_dd to a source terminal of a transistor turns the transistor OFF, while applying GND to a source terminal turns it ON. Thus, one can selectively control the ON/OFF state of a transistor. The ON transistors are used to generate heat, while the OFF transistors are used to measure the temperature rise due to spread-heating from the subthreshold slope. The analysis of the measurements from these structures is expected to be complete by the end of 2006.

The electrical integrity of devices and circuits must be preserved during the 3D IC fabrication process. One critical issue is the effect of thermal cycling and mechanical stresses brought on by the layer transfer processes during 3D IC fabrication. Another issue relates to the precise alignment and low parasitic connection requirements for stacking and interconnecting the multiple device layers. To obtain the optimal circuit benefit, the alignment and interconnect dimensions must be of the order of that in the critical layers, and the layer transfer process cannot degrade the performance of the 3D structures. The IBM performance-integrity test structures include ring oscillators (ROs), single transistors (FETs), and inverter circuits. We performed a systematic study of the electrical integrity of high-performance SOI FETs (of various geometries, down to length L = 55 nm) and ring oscillator (RO) circuits that were subjected to the processes required for layer transfer.

In the first testing stage each wafer was put through several stages of the layer-transfer process, and electrical tests were performed on 25 chips per wafer after each stage for the top device layer transferred onto another device layer without the interconnection process. Among other measurements [16], we examined median data for a particular wafer at three stages: a) after standard CMOS fabrication; b) after an additional “simulated” lamination process in which the pressure and temperature required to adhere the processed wafer to glass are applied without actually completing the adhesion; c) after full attachment to glass, an anneal to simulate the thermal processing required for the second bonding step, and elimination of the glass plus adhesive removal. Linear drain current, I_dlin, and linear threshold voltage, V_tlin, of long-channel (5-μm) n-FETs were not appreciably altered, indicating that these processes do not influence the channel mobility. The short-channel (65-nm) devices show a slight (<10%) degradation in I_dlin and V_tlin, which we attribute to an increase in line resistance, since small devices are more sensitive to resistance changes [16].

Once the process was optimized to preserve the resistance characteristics of the top circuits, special masks were designed in order to be able to build 3D IC circuits with functional top and bottom device layers after the layer transfer process. First, V_tlin and saturation voltage, V_tsat, were measured for various FETs on the bottom layer of two-layer stacked ICs. Figure 15 shows the V_t plots for the same six locations on the wafers from the same lot before and after the layer transfer and interconnection process. Data indicates that, within the statistical margins, no degradation due to the 3D IC layer transfer process has been detected.

Figure 15

ROs with 59 or 41 ring stages, a 13-stage divider, and a five-stage output buffer were designed and fabricated. There are seven macros with 3D ROs and inverters. The variation in 3D RO layout is related to the placement of n-MOS or p-MOS transistors on the top or bottom wafer. The 41-stage RO allows a bonding misalignment of 2 μm with the use of a large landing zone for interwafer vias. The 59-stage RO requires strict bonding alignment (~0.5 μm). In addition, process conditions during the patterning of the gates were tuned to enable the creation of RO devices of various lengths. As depicted in Figure 16, the lithographic exposure dose affects the length of the gate and therefore changes RO delay. Trends show that a higher dose yields more process variation, while a lower dose gives better process control. Overall, the performance of the RO on the bottom layer appears to be unaffected by the layer-transfer process [32].

Figure 16

This paper reviews various 3D integration technologies, addresses key integration challenges of the 3D ICs, and describes several optical and electrical test structures fabricated to verify 3D IC process readiness. A critical need exists for a reliable layer-to-layer alignment accuracy; several techniques for alignment and overlay measurements have been presented. The most aggressive alignment tolerance (0.18 μm) for 3D ICs can be achieved by implementing a transparent substrate, high-quality oxide fusion bonding, and bow compensation methods. Further process improvement of alignment across the wafer is needed.

We have described issues related to the fabrication of small, high-aspect-ratio vias suitable for high-density connections between layers in a 3D IC. Using 0.13-μm MOSFET and ring oscillator circuits, it was shown that BEOL CMOS process techniques can be used to fabricate copper-filled, high-aspect-ratio (>8:1) trenches, providing the capability to create the smallest (sub-μm-size) vias as wafer-to-wafer connections. Electrical structures for testing the reliability of the connecting vias and bonding interface have been reviewed. Test structures for characterizing both self- and spread-heating effects in 3D ICs have also been described. This work is a major step toward the realization of true wafer-level 3D integration of high-performance CMOS devices.

The authors are indebted to their many collaborators at IBM for the results described in this paper. In particular, we thank W. Haensch, J. Patel, J. Vichiconti, S. Goma, D. Dimilia, D. Posillico, M. Cobb, S. Medd, M. T. Robson, E. Duch, M. Farinelli, D. Boyd, D. Neumayer, C. Wang, R. A. Conti, D. M. Canaperi, L. Deligianni, K. T. Kwietniak, C. D'Emic, J. Ott, K. Jenkins, R. Joshi, N. Zamdmer, and Prof. J. Lu from RPI for their collaborations and useful discussions. Many colleagues kindly provided data and information for this paper, and these are cited individually in the references. The devices and circuits were fabricated at the IBM Advanced Semiconductor Technology Center, the Materials Research Laboratory, and Central Scientific Services; and we thank the facility management team for strong support for this project. This material is based upon work supported in part by DARPA under SSC SAN DIEGO Contract Nos. N66001-00-C-8003 and N66001-04-C-8032.

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¹Edward Nowak, IBM Systems and Technology Group, personal communication, 2003.

Received September 22, 2005; accepted for publication April 26, 2006; accepted for publication August 8, 2006;