Germanium channel MOSFETs: Opportunities and challenges

MOSFETs with a high-mobility channel are attractive candidates for advanced CMOS device structures, since it is becoming increasingly difficult to enhance Si CMOS performance through traditional device scaling. The lower effective mass and higher mobility of carriers in germanium (Ge) compared with silicon (Si) (2x higher mobility for electrons and 4x for holes) has prompted renewed interest in Ge-based devices for high-performance logic. Ge channel MOSFETs have been identified as one of the possible directions for channel engineering [1].

Recently, surface-channel Ge MOSFETs have been demonstrated using thin Ge oxynitride [2] or high-k dielectric [3–5] as the gate insulator. However, most of the devices reported have used relatively simple structures such as a ring-type gate structure for simplified integration, and devices usually have relatively large dimensions. In addition, the low bandgap of germanium (0.67 eV compared with 1.12 eV for Si) presents a device design challenge, while the much lower melting point (934°C compared with 1,400°C for Si) presents additional processing challenges for integrating Ge channel MOSFETs. To demonstrate state-of-the-art Ge channel devices, several key issues have to be addressed. This paper reviews the major integration challenges and mobility enhancement associated with Ge surface-channel devices as well as strained Ge/SiGe channel devices.

Gate dielectric
One major problem for Ge CMOS device fabrication is that it is very difficult to obtain a stable oxide gate dielectric. The water-soluble native Ge oxide that is typically present on the upper surface of a Ge-containing material causes this gate dielectric instability.

The best known dielectric candidate for use on Ge is Ge oxynitride (GeO_xN_y). High-quality thin GeO_xN_y can be formed on germanium by nitridation of a thermally grown germanium oxide. Rapid thermal oxidation (RTO) at 500–600°C followed by rapid thermal nitridation (RTN) at 600–650°C in ammonia (NH₃) ambient has generally been practiced. NH₃ is chosen as the nitriding agent because of its ability to incorporate more nitrogen into the oxynitride film than other nitriding species, such as nitrous oxide (N₂O) and nitric oxide (NO). By using this method, the resulting film thickness can be scaled down to an effective oxide thickness (EOT) as thin as 1.9 nm with acceptable leakage; the refractive index is found to be about 1.3–1.5 [6]. GeO_xN_y has better thermal and chemical stability than native Ge oxides (GeO and GeO₂) [7, 8]. In addition, the incorporation of nitrogen into Ge oxides could reduce the potential interdiffusion between the gate dielectric and substrate and/or the gate electrode. High-performance Ge MOSFETs with greater mobility than Si MOSFETs with SiO₂ were demonstrated using a relatively thick GeON (EOT ~5 nm) [2, 9]. However, the most important application for high-quality thin GeO_xN_y is perhaps that it could serve as a stable interlayer for the integration of novel high-k dielectrics into Ge MOS devices.

The recent development of high-quality techniques [e.g., atomic layer deposition (ALD) and metal–organic chemical vapor deposition (MOCVD)] for deposition of dielectric films with high dielectric constants (4.0; typically 7.0) to replace SiO₂ in Si MOSFETs has prompted activities to develop Ge MOSFETs implementing such dielectrics. Binary metal oxides (e.g., ZrO₂, HfO₂) have been the primary choices as high-k gate dielectrics. In addition, germanates (MeGe_xO_y, where Me stands for a metal with high ion polarizability, such as Hf, Zr, La, Y, Ta, and Ti) have also been proposed to potentially improve carrier mobility and interface stability.

Surface preparation and interface control
One of most challenging tasks for Ge/high-k MOS systems is the Ge surface preparation and interface control before high-k film deposition.

For Ge specifically, it appears essential to have a surface free (i.e., devoid) of germanium oxide before high-k film deposition. A conventional solution for Si has been to use concentrated or dilute hydrofluoric acid (i.e., HF or DHF) to remove any native Si oxide while leaving an H-passivated surface. Despite being successful for the fabrication of Si CMOS devices, this surface-passivation technique was found to be less effective on Ge [10].

One demonstrated method of fabricating functional gate stacks is to desorb the Ge oxide in an ultrahigh-vacuum (UHV) system at high temperatures (e.g., 400–650°C) followed by in situ high-k deposition [11, 12]. The main drawback of this approach is that UHV systems are costly and are generally incompatible with the standard ALD or MOCVD high-k deposition tools used in manufacturing. A practical solution is based on nitridation of a wet-etched (e.g., using DHF) Ge surface prior to dielectric deposition using either atomic N exposure [12] or a high-temperature NH₃ gas treatment [5, 13–16].

We found both the microstructure of the high-k film deposited on Ge and the electrical properties of Ge/high-k MOS capacitors to be very sensitive to the Ge surface preparation prior to high-k film deposition [14]. In our study, the Ge surface is first wet-cleaned, and then HfO₂ is deposited on the Ge substrate by ALCVD. It is interesting that HfO₂ grows epitaxially [Figure 1(a)] on the wet-cleaned Ge surface with deionized (DI) H₂O as the last process step, while amorphous HfO₂ [Figure 1(b)] is observed on the Ge surface treated with nitrogen passivation by RT NH₃ processing (at 650°C for one minute), as shown in Figure 1. Figure 2 shows the C–V characteristics of MOS capacitors for both cases. In contrast to the large frequency dispersion observed in the DI-water-processed sample, very little frequency dispersion was observed for the sample with nitrogen passivation. The large dispersion is probably caused by Ge–Hf bonding or interdiffusion at the Ge–HfO₂ interface, which may have been effectively reduced in the case of nitrogen passivation by RT NH₃ before HfO₂ deposition. However, hysteresis still remains, and additional traps are introduced during the RT NH₃ process. The nitridation step also induces fixed positive charge at the interface, which causes a large negative flat-band shift and could degrade the device mobility.

Figure 1 Figure 2

Several research groups have recently reported that effective passivation can be achieved by using SiH₄ [17]. An EOT as thin as 0.75 nm was reported with a plasma PH₃ treatment and thin AlN layer [18] combined with a HfO₂/TaN gate stack. In addition to the above-mentioned physical passivation methods, novel wet chemistries are also being studied to passivate the Ge surface during pre-clean. Clorine-passivated [19] and sulfur-passivated [20] Ge surfaces are two examples.

Although much technological progress has been made on this subject, greater understanding and a well-controlled Ge surface are needed for successful application of high-k dielectrics on Ge MOS devices.

Gate electrodes
Because of the low melting point of Ge, it is desirable to use metal gate electrodes rather than conventional polySi gate electrodes where high-temperature (>900°C) dopant activation is required. Metal materials such as Al, W, Pt, TiN, and TaN are among the most popular metal electrodes reported for Ge MOSFETs [2, 5, 16]. Although the criteria for metal gate electrodes are similar to those for Si MOSFETs, the interaction of metal electrodes with the Ge gate dielectric must be considered. One of the examples is the Ge/GeON MOS capacitors with aluminum (Al) and tungsten (W) gate electrodes. A much thinner EOT can be obtained by using tungsten rather than aluminum as the gate electrode because of the elimination of the interfacial layer formed between GeON and Al [15].

The diffusion of p-type dopants such as boron is suppressed while the diffusion of n-type dopants such as P, As, and Sb is enhanced in SiGe and Ge compared with bulk Si [21]. This favors the formation of ultrashallow junctions in p-channel Ge MOSFETs, while presenting a challenge for shallow-junction formation in n-channel Ge MOSFETs. Methods such as co-implantation have been demonstrated to show that As diffusion in 20–75% SiGe can be reduced 2.5 to 3.7 times [21]. An alternative method based on solid-phase diffusion was reported for attempts to form a shallow n-type junction in Ge [22]. Despite a few reported n-channel Ge MOSFETs [23], the dopant solubility limit and rapid dopant diffusion are believed to be the major reasons for the relatively poor performance observed in recently reported n-channel Ge MOSFETs [24].

The smaller bandgap in Ge has been a concern because of its influence on junction leakage and band-to-band tunneling. The junction leakage of both n⁺/p and p⁺/n Ge diodes formed by boron and phosphorus implantation can be reduced to ~10⁻⁴ A/cm² with annealing. This is considered acceptable for device operation.

On extremely scaled MOSFETs, band-to-band tunneling is a great concern [25]. The band-to-band tunneling current increases exponentially in smaller-bandgap semiconductors and could thus be a more serious issue for Ge MOSFETs. It has been shown that the band-to-band tunneling can be reduced dramatically through careful device structure design. A detailed study of its impact on Ge MOSFET scaling can be found in [26].

For conventional self-aligned Ge MOSFET fabrication (i.e., a standard fabrication sequence, not a replacement-gate approach), the gate stack must maintain its integrity throughout the source/drain (S/D) junction anneal. The p-channel Ge MOSFETs have been consistently demonstrated with up to 2x hole mobility enhancement over Si devices. A discussion of state-of-the-art hole-mobility enhancement in recent reported Ge channel p-MOSFETs can be found in [27]. On the other hand, n-channel Ge MOSFETs pose a particular fabrication challenge: There is a relatively small process window to jointly achieve a stable gate stack, a well-activated n⁺ S/D, and a low-resistance ohmic contact because of the low dopant solubility in Ge [28] and dopant outdiffusion during activation.¹

By adding a high-quality thin layer of Si on top of Ge, a good-quality Si/SiO₂ interface can be achieved. In addition, Si-based gate dielectric and high-k films can be applied on the devices. Combined with a strained-Ge (s-Ge) channel grown on top of relaxed SiGe, the s-Ge buried-channel devices are expected to have improved mobility due to the very small effective hole mass (<0.1m₀) in the s-Ge layer [29] and the reduced surface roughness scattering. Indeed, dramatic hole-mobility enhancement of 4–25x has been demonstrated in s-Ge-channel MOSFETs [30–34]—the highest mobility enhancement for hole carriers among all available options. On the other hand, one of the major concerns for buried-channel devices has been the device scalability.

It is known that the effective gate dielectric thickness in buried-channel devices is increased when compared with surface-channel operation, resulting in worse short-channel effects, such as a larger subthreshold swing and V_t roll-off. Thus, the s-Ge buried-channel device must be carefully designed and evaluated to ensure greater performance without short-channel degradation [34].

To achieve maximum performance in the s-Ge buried-channel MOSFETs, most carriers must be confined within the high-mobility s-Ge layer. For heavily doped channel structures, it is found that the carrier confinement is strongly dependent on the Si cap thickness. By using a retrograde doping profile, short-channel characteristics similar to those found in bulk Si surface-channel devices can be achieved on strained-Ge buried-channel MOSFETs. The details can be found in [34].

There are two main techniques to obtain a strained-Ge or high-Ge-content SiGe layer: chemical vapor deposition (CVD) or Ge condensation (also called thermal mixing [30]). Both ultrahigh-vacuum (UHV) CVD and plasma-enhanced CVD (PECVD) methods have been reported for strained-Ge growth [30, 31, 34].

The low-temperature UHV–CVD technique allows fine control of the thickness of both the strained-Ge layer and the Si cap layer. In our experiment, the growth of the strained-Ge buried-channel structure begins with a relaxed ~75% SiGe buffer followed by an s-Ge channel (13 nm) and an ultrathin Si cap (1.5 nm). Cross-sectional transmission electron microscopy (XTEM) shows the high quality and atomic abruptness of both the Si cap/Ge and Ge/SiGe interfaces. Atomic force microscopy (AFM) results (RMS = 6.7 nm) show a relatively smooth surface, which can be further improved by applying an intermediate chemical–mechanical polishing (CMP) to smooth the SiGe buffer layer [30, 31]. Triple-axis X-ray diffraction measurements were used to quantify the strain in the Ge channel and the Ge content and strain relaxation of the SiGe buffer layer. Strain relaxation during the device fabrication is a major concern. We measured the strain of the s-Ge channel after furnace anneals at temperatures from 550°C to 700°C for 30 min. As shown in Figure 3, virtually no strain relaxation is observed after annealing up to 600°C, but there is significant relaxation at 650°C and above. This sets the upper limit of the s-Ge-channel device processing temperatures. For a rapid thermal anneal (RTA) of this structure, the strain-relaxation trend is similar to the furnace anneal results.

Figure 3

Achieving a high-quality thin-gate dielectric for s-Ge-channel MOSFETs has proven challenging as well. As shown above, to maintain the strain in the s-Ge channel, all processing temperatures should be kept below 600°C [34]. Because of this constraint, low-temperature-deposited high-k dielectrics and silicon dioxide low-temperature oxide (LTO) were used as the gate dielectrics of s-Ge-channel MOSFETs [30–34].

We have developed a new low-temperature (400°C) remote plasma oxide as the gate dielectric for UHVCVD-grown s-Ge channel MOSFETs. This technique enables us to achieve the thinnest high-quality Si oxide ever reported on Ge. Figure 4(a) shows the typical C–V characteristics of MOS capacitors with EOT  3 nm remote plasma oxide on Si. Figure 4(b) shows the interface trap density, D_it, measured using the conductance (G) method, where D_it is ~2.5 × 10¹⁰/cm²-eV, which is very close to the value measured on MOS capacitors with ~3 nm thermal SiO₂. Similar leakage current is found on the remote plasma oxide MOS capacitors on both Si and UHV strained-Ge samples. The high-quality, low-temperature remote plasma oxide is essential for achieving high-performance s-Ge-channel p-MOSFETs with thin SiO₂ as the gate dielectric.

Figure 4

Although much work has been performed to demonstrate great hole-mobility enhancement in s-Ge-channel p-MOSFETs using simple structures to avoid complicated processing issues, a compatible process to incorporate s-Ge structures into standard CMOS technology is needed. One of the proposed ideal CMOS structures is shown in Figure 5, where p-MOSFETs employ a buried s-Ge channel, while n-MOSFETs employ a Si or strained-Si surface channel. This structure requires that a thin s-Ge channel be formed selectively on only p-MOSFET regions [35].

Figure 5

In our work, we use silicon germanium oxide insulator (SGOI) substrates with ~30% Ge as the starting material. A standard shallow-trench isolation (STI) process is performed to form SGOI active regions. An optional patterning step can be used to mask the n-MOSFET regions with oxide or nitride. Two techniques can be used to form a strained-Ge channel selectively on the patterned SGOI regions using 1) local thermal mixing (LTM): high-temperature oxidation to enrich the Ge content in the SGOI layer—TM Ge; or 2) a selective UHVCVD process: growth of a strained Ge layer with a thin Si cap using UHVCVD—UHV Ge. In the TM Ge sample, the Ge fraction is found to be ~67%, with 1.47% compressive strain as measured by X-ray diffraction (XRD) analysis. In addition, medium-energy ion scattering (MEIS) analysis shows that the Ge content in the SGOI layer after local thermal mixing is ~60%. For the UHV Ge sample, cross-section SEM confirmed the selectivity of the s-Ge-layer growth, such that s-Ge is formed only on top of the SiGe and not on the STI regions (oxide).

After the s-Ge layer is formed, a conventional CMOS process is used for device fabrication, including gate stack formation, source/drain (S/D) implants, and metal contacts. For both UHV Ge and TM Ge device fabrication, we use in situ boron-doped polySi as the gate electrode.

TM Ge with HfO₂ gate oxide
For TM Ge MOSFETs, the surface is first treated using RT NH₃; then ~6.5 nm HfO₂ is deposited by MOCVD at 500°C as the gate dielectric. Figure 6 is a TEM image of the TM Ge device showing the HfO₂ gate dielectric under the polysilicon gate.

Figure 6

Figures 7(a) and 7(b) show the linear current and subthreshold characteristics of the TM Ge p-MOSFETs with HfO₂ gate oxide, along with the Si control. The channel length of each device is 10 μm. Performance enhancement of ~2.5x is observed in both linear and saturation regimes. The subthreshold slope is ~125 mV/dec in TM Ge and ~98 mV/dec in the Si control. The threshold voltage in the linear region (V_tlin) is extracted using the constant current at 70 nA/μm. We found that the value of V_tlin in the Si/HfO₂/polySi control is ~−0.67 V. In contrast, the V_tlin value from the TM Ge device is found to be approximately −0.36 V, which is ~300 mV lower than that in the Si/HfO₂/polySi control.

Figure 7

One of the most important issues with respect to Si/HfO₂/polySi p-MOSFETs today is the high V_th value due to the Fermi-level pinning [36]. Because of the valence-band offset, the Ge channel allows the V_th of HfO₂/polySi p-MOSFETs to be lowered to the appropriate V_th for high-performance CMOS technology.

UHV Ge with SiO₂ gate oxide
For UHV Ge MOSFETs, high-quality SiO₂ as thin as 2.5 nm is achieved on s-Ge with a thin Si cap by using low-temperature remote plasma oxidation. Figure 8 is a TEM image of the UHV Ge device showing 2.5 nm SiO₂ under a polysilicon gate. Figures 9(a) and 9(b) respectively show the linear current and subthreshold characteristics of the UHV Ge p-MOSFETs with SiO₂ gate oxide formed by remote plasma, along with the Si control. The channel length of each device is 10 μm; ~3x drive current is observed in both linear and saturation regimes. The larger enhancement in UHV Ge devices could be due to the higher Ge content (100% vs. 60%) in the channel and a SiO₂-based gate dielectric. On the other hand, higher subthreshold leakage current is found on the UHV Ge p-MOSFETs. This is probably due to the growth defects in the s-Ge layer and may be improved by process optimization.

Figure 8 Figure 9

It is worth pointing out that device performance enhancement over Si controls is demonstrated because of the significantly enhanced hole mobility.

Surface passivation and gate dielectric, dopant diffusion, and junction leakage are the three most serious challenges associated with Ge CMOS devices. By using the s-Ge with an ultrathin Si cap, standard Si surface passivation and gate dielectric can be applied without significant modification. Table 1 compares s-Ge buried-channel MOSFETs with Ge surface-channel devices. An s-Ge buried-channel device can be integrated with fewer processing challenges, significantly higher hole mobility, and improved electron mobility. These results indicate that the s-Ge buried-channel MOSFET with an ultrathin Si cap is a promising option for future scaled CMOS devices. We show a CMOS-compatible integration scheme for strained-Ge-channel p-MOSFETs, including the conventional STI isolation and scaled thin gate dielectrics for high-performance CMOS technology. Although it is a major step toward integrating strained-Ge channels into CMOS technology for continued performance enhancements, much work remains to be done in the demonstration of state-of-the-art short-channel Ge p-MOSFETs with sufficient performance enhancement.

The authors would like to thank the IBM Thomas J. Watson Research MRL and CSS facilities for their help in device fabrication. In addition, we wish to thank Dr. Ghavam Shahidi and Dr. T.-C. Chen for managerial support. One of the authors would like to thank Dr. H.-S. Philip Wong for valuable discussions and initial encouragement.

¹Private data, to be published.

Received October 10, 2005; accepted for publication April 18, 2006; Published online June 28, 2006.