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IBM Journal of Research and Development
Advanced Silicon Technology   Volume 50, Number 4/5, 2006
Table of contents: HTMLPDF This article: HTMLPDF   Copyright info

Product-representative “at speed” test structures for CMOS characterization - References

 by M. B. Ketchen
and M. Bhushan
References

  1. J. S. Panganiban, “A Ring Oscillator Based Variation Test Chip,” M. Eng. Thesis, Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology, Cambridge, MA, May 2002.
  2. B. E. Stine, E. Chang, D. S. Boning, and J. E. Chung, “Analysis and Decomposition of Spatial Variation in Integrated Circuit Processes and Devices,” IEEE Trans. Semicond. Manuf. 10, 24–41 (1997).
  3. A. Bassi, A. Vegetti, L. Croce, and A. Bogliolo, “Measuring the Effects of Process Variations on Circuit Performance by Means of Digitally-Controllable Ring Oscillators,” Proceedings of the IEEE International Conference on Microelectronic Test Structures, 2003, pp. 214–217.
  4. M. Ketchen, M. Bhushan, and D. J. Pearson, “High Speed Test Structures for In-Line Process Monitoring and Model Calibration,” Proceedings of the IEEE International Conference on Microelectronic Test Structures, 2005, pp. 33–38.
  5. M. Bhushan, A. Gattiker, M. Ketchen, and K. K. Das, “Ring Oscillators for CMOS Process Tuning and Variability Control,” IEEE Trans. Semicond. Manuf. 19, 10–18 (2006).
  6. Y. Taur and T. H. Ning, Fundamentals of Modern VLSI Devices, Cambridge University Press, Cambridge, UK, 1998, Ch., 5.
  7. N. H. E. Weste and K. Eshraghian, Principles of CMOS VLSI Design, Addison-Wesley Publishing Co., New York, 1992, p. 366,–pp. 465–506.
  8. S. Polonsky, M. Bhushan, A. Gattiker, A. Weger, and P. Song, “Photon Emission Microscopy of Inter/Intra Chip Device Performance Variations,” Microelectron. Reliabil. 45, 1471–1475 (2005).
  9. D. K. Schroder and J. A. Babcock, “Negative Bias Temperature Instability: A Road to Cross in Deep Submicron CMOS Manufacturing,” J. Appl. Phys. 94, 1–18 (2003).
  10. A. Asenov, A. R. Brown, J. H. Davies, S. Kaya, and G. Slavcheva, “Simulations and Intrinsic Parameter Fluctuations in Decananometer and Nanometer-Scale MOSFETS,” IEEE Trans. Electron Devices 50, 1838 (2003).
  11. B. P. Wong, G. Starr, G. Starrett, A. Mittal, and Y. Cao, Nano CMOS Circuit and Physical Design, John Wiley and Sons, Inc., New York, 2004.
  12. C. Kothandaraman, S. K. Iyer, and S. S. Iyer, “Electrically Programmable Fuse (eFuse) Using Electromigration in Silicides,” IEEE Electron Device Lett. 23, 523–525 (2002).
  13. M. Bhushan, K. Chandrasekara, M. Ketchen, and E. Maciejewski, “Method and Apparatus for Characterizing Electronic Fuses Used to Personalize an Integrated Circuit,” U.S. Patent filed (IBM Docket No. YOR920040458US1), 2005.
  14. S. K. H. Fung, N. Zamdmer, P. J. Oldiges, J. Sleight, A. Mocuta, M. Sherony, S.-H. Lo, R. Joshi, C. T. Chuang, I. Yang, S. Crowder, T. C. Chen, F. Assaderaghi, and G. Shahidi, “Controlling Floating-Body Effects for 0.13 μm and 0.10 μm SOI CMOS,” IEDM Tech. Digest, pp. 231–232 (2000).
  15. S. Polonsky and K. A. Jenkins, “Time-Resolved Measurements of Self-Heating in SOI and Strained Silicon MOSFETs Using Photon Emission Microscopy,” IEEE Electron Device Lett. 25, 208–210 (2004).
  16. K. A. Jenkins, J. Y.-C. Sun, and J. Gautier, “Characteristics of SOI FETs Under Pulsed Conditions,” IEEE Trans. Electron Devices 44, 1923–1930 (1997).
  17. M. Ketchen, M. Bhushan, and K. A. Jenkins, “Circuit to Measure High Speed Pulse I-V Characteristics with Only DC I/Os,” Proceedings of the IEEE International SOI Conference, 2005, pp. 77–78.
  18. D. J. Pearson, M. B. Ketchen, and M. Bhushan, “Technique for Rapid, In-Line Characterization of Switching History in Partially Depleted SOI Technologies,” Proceedings of the IEEE International SOI Conference, 2004, pp. 148–150.
  19. M. B. Ketchen, M. Bhushan, and C. J. Anderson, “Circuit and Technique for Characterizing Switching Delay History Effects in Silicon on Insulator Logic Gates,” Rev. Sci. Instrum. 75, 768–771 (2004).
  20. M. B. Ketchen and M. Bhushan, “Anomalous History Behavior in Stacked PD SOI Gates,” Proceedings of the IEEE International SOI Conference, 2003, pp. 168–169.
  21. M. B. Ketchen, M. Bhushan, and S. Bermon, “Switching Delay Variability in NMOS and PMOS PD–SOI Passgate Circuits,” Proceedings of the IEEE VLSI–TSA International Symposium on VLSI Technology, 2005, pp. 68–69.


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