Ultralow-voltage, minimum-energy CMOS

Mobile battery-powered electronic devices have created a growing demand for energy-efficient circuit design. Cellular phones alone represent a large industry and create both an opportunity for innovation and the potential for profitability. Future progress in mobile electronics will depend on the development of inexpensive devices with complex functionality and long battery life. The aim of this paper is to show how devices, circuits, and architectures within this design space may be optimized for minimum energy consumption.

Even in the realm of high-performance microprocessors, power has become a limiting constraint. Traditional scaling of high-performance FETs uses a combination of supply-voltage (V_dd) and threshold-voltage (V_th) reduction to accommodate both performance and power requirements, but the rapid rise of subthreshold and gate leakage has placed limits on this scaling strategy. It is clear that new strategies are necessary to address the power concerns in high-performance designs.

Voltage scaling is the most effective solution to stringent power requirements and has been practically demonstrated in a number of designs. Reduction of the supply voltage (with a fixed threshold voltage) results in a quadratic reduction of dynamic energy at the expense of decreased performance. For many applications, this performance penalty is tolerable. In fact, for a wide range of applications, including sensors and medical devices, a significant performance penalty may be tolerated without compromising the usefulness of the device. High-performance designs may also take advantage of supply-voltage reduction during idle periods when the circuit is performing simple background routines, because performance requirements are relaxed or removed altogether. Regardless of the application, the use of aggressive voltage scaling can lead to considerable energy reductions whenever performance demands are low for a circuit.

This paper explores the limits of minimum-energy CMOS. We show that, for large classes of circuits, minimum energy consumption occurs when the voltage is scaled below the device threshold voltage. In this region, called the subthreshold (sub-V_th) regime, energy consumption can be reduced by 20x relative to standard superthreshold (V_dd > V_th) operation. We use a hierarchical approach to the exploration of sub-V_th design. We begin by discussing the evolution of device behavior as supply voltage is reduced into the sub-V_th regime. We then develop intuition and a methodology for minimum-energy design by considering circuit behavior in the sub-V_th regime. Finally, we use this intuition to discuss how architectural techniques may be used to improve energy efficiency in designs dedicated to low-energy operation as well as designs with both performance and energy requirements.

At the device level, we compare FET sub-V_th and super-V_th characteristics and sensitivities. We find that sub-V_th FET currents are exponentially dependent on V_th and V_dd and that this presents the biggest challenge to device, circuit, and architecture design. In a design that must operate over a wide range of voltages and performance levels, minor tradeoffs, such as lengthening FET channels slightly to reduce V_th variation and making minor V_th adjustments to maintain nominal matching between FETs at low V_dd, should be considered. However, if energy minimization at low V_dd is the critical goal, significant device-optimization studies must be considered. Dual-gate FETs show much promise for future work in energy-optimal design. If combined with low-workfunction metal gates and an increased channel length, dual-gate FETs can help minimize V_th variations and achieve a steep sub-V_th slope, the key parameters for sub-V_th operation.

At the circuit level, we present a simple analytical model for the energy-optimal supply voltage, V_min. This simple model illustrates the tradeoff between leakage energy and dynamic energy that occurs in energy-optimal circuits. We find that energy efficiency is limited by the rise of leakage and that the designers of energy-efficient circuits should reduce V_min until it approaches V_dd,limit, the minimum functional voltage. Additionally, we find that heightened sensitivity to the threshold voltage in combination with a low I_on/I_off ratio results in serious circuit-level robustness concerns when process variation is being considered. Energy efficiency also exhibits a strong sensitivity to threshold variability.

We pay special attention to SRAM arrays. We find that large SRAM arrays have higher V_min and V_dd,limit values than those used for standard logic. For a standard six-transistor SRAM (6T-SRAM) array, V_dd,limit is shown to be higher than V_min, suggesting that significant redesign will be necessary to produce robust, energy-efficient SRAM design. The problem is further complicated by process variation, particularly V_th mismatch introduced by random dopant fluctuations. The eight-transistor SRAM (8T-SRAM) cell is presented as a feasible solution.

In the final section of the paper, we discuss energy-efficient architectural techniques. We suggest that techniques such as multi-threshold CMOS (MTCMOS), adaptive body biasing (ABB), and the use of voltage islands can help a design achieve energy optimality by shifting V_min toward V_dd,limit. Architectural techniques, specifically those that involve multiprocessor design, can ameliorate the performance penalty suffered as a result of low-voltage operation.

The paper is organized as follows. In Section 2 we discuss device-level behavior at sub-V_th and near-V_th voltages. Section 3 includes a discussion of the implications of device-level changes at the circuit level and a general and useful energy model for sub-V_th operation. The complications introduced by SRAM design are given special consideration. Finally, in Section 4 we discuss energy-efficient architectural techniques targeted at both dedicated minimum-energy operation and high-performance operation.

As V_dd is reduced to minimize energy per operation, FETs make the transition from superthreshold (super-V_th) operation in strong inversion with large gate overdrives, to near-V_th operation in weak inversion with very small overdrives, and finally into sub-V_th operation. Sub-V_th operation differs from super-V_th operation primarily because the sub-V_th on-current (I_on-sub) depends exponentially on threshold voltage (V_th) and power-supply voltage (V_dd), while the typical super-V_th operation on-current (I_on-super) depends roughly linearly on V_th and V_dd. The I_on-sub exponential sensitivities to V_th and V_dd are captured in the following equation:

(1)

where v_T = kT/q. In these equations, T is temperature, v_T is the thermal voltage, k is Boltzmann's constant, q is the charge of an electron, L_eff is the effective gate length, μ_eff is the effective mobility, C_ox is the oxide capacitance, W is the gate width, and m is the subthreshold slope factor. On-current is defined in this paper as I_ds, when V_gs = V_ds = V_dd. It is important to highlight the implicit V_th dependence on L_eff in Equation (1) because I_on-sub becomes very sensitive to L_eff due to the V_th term. V_th is also dependent on V_ds via drain-induced barrier lowering (DIBL), which plays a role in determining the effect V_dd has on I_on-sub. The linear sensitivity of I_on-super to V_th and V_dd for short-channel FETs is captured in the equation

(2)

where R_s is the FET source resistance and g_msat is the saturated transconductance, which depends on L_eff, C_ox, and the carrier saturation velocity. V_PO is the pinch-off voltage. The near-V_th I_on sensitivity to V_th and V_dd is bounded by the sub-V_th and super-V_th sensitivities. Figure 1 highlights the differences between super-V_th and sub-V_th current characteristics. Tables 1 and 2 compare key parametric sensitivities of FETs in sub-V_th, near-V_th, and super-V_th operation.

Figure 1

The exponential sub-V_th I_on sensitivity to V_th drastically affects circuit behavior. First, the circuit delay and power now also depend exponentially on V_th and V_dd. More significantly, current matching between two FETs is exponentially dependent on any difference in V_th. For example, while a reasonable 6σ 100-mV V_th mismatch disturbs the FET current ratios by only approximately 1.17x in super-V_th operation, a similar 100-mV V_th mismatch upsets the current matching by greater than 10x in sub-V_th operation. (We use “x” throughout this paper to indicate “times,” so that, for example, “10x” means a factor of 10 times.) This extreme sensitivity to V_dd and V_th presents the most significant challenge to sub-V_th and near-V_th circuit functionality, and is discussed in later circuit sections.

Product requirements dictate how device optimizations may be used to increase energy efficiency. One product application may have performance restrictions and will therefore be required to operate at high V_dd. In this case, it is likely that the process will be similar to a typical super-V_th process. A multiple-core microprocessor may be an example of such an application, in which the V_dd of each core is varied according to performance needs and power constraints during operation. In this scenario, a few key circuits may require modification to enable low-voltage operation, but the potential to minimize energy is ultimately limited by the high-performance requirements. There may also be some small technology modifications (e.g., small V_th adjustments) that enable low-V_dd operation without a significant high-V_dd performance impact. On the other hand, if the application is aimed solely at low-V_dd operation, the technology and circuits can be optimized to minimize total energy consumption. A number of techniques for addressing these two very different scenarios at the architectural level are discussed in Section 4. In this section, we first consider FET low-V_dd characteristics and sensitivities that have implications for both of these scenarios.

The exponential sensitivity to V_th in sub-V_th and near-V_th operation changes the impact that key device parameters have on FET currents (see Tables 1 and 2). For example, a 10% reduction in inverse sub-V_th slope increases sub-V_th I_on by 1.7x and super-V_th I_on by only 3% (sub-V_th slope measures the slope of the drain current with respect to gate voltage and is commonly quoted in its inverse form in mV/decade). As a result, sub-V_th I_on is much more sensitive to FET gate insulator thickness, t_ox, because t_ox plays a critical role in determining the sub-V_th slope. In typical high-performance technologies, FET channels are made as short as possible, and as a consequence sub-V_th slope is suboptimal. Reducing t_ox improves the sub-V_th slope and significantly increases sub-V_th I_on. The impact of the sub-V_th slope improvement in super-V_th I_on is considerably less. In reality, the observed super-V_th I_on increase results from the sublinear saturated transconductance dependence on t_ox. (Transconductance is an expression of the current-carrying ability of a FET. In general, the larger the transconductance value for a device, the greater the gain it is capable of delivering.) The example in Table 2 shows that a 1.3x reduction in t_ox improves the sub-V_th I_on by 1.7x and improves the super-V_th I_on by only 1.23x. The authors of [1] show that improved sub-V_th slope makes a significant contribution to the energy savings observed in devices optimized for sub-V_th operation. As we see in Section 3, the leakage reduction resulting from sub-V_th slope improvement provides an attractive strategy for energy minimization.

The impact of FET channel length (L_gate) on sub-V_th I_on is due predominantly to the dependence of V_th and the sub-V_th slope on L_gate. At short channels, V_th decreases and sub-V_th slope degrades as the value of L_gate is reduced because of drain barrier lowering and other short-channel effects. As a consequence, the sub-V_th current increases exponentially at short L_gate values, as shown in Figure 2 for an n-FET in a typical 65-nm technology. Typically, high-performance FETs use L_gate in the region where these parameters vary strongly with length. This creates a considerable challenge for sub-V_th operation because small variations in L_gate values have an enormous impact on I_on. In particular, L_gate linewidth variation leads to significant mismatch in FET drive strengths. This effect can be reduced by increasing values of L_gate (Figure 3 shows I_on variation resulting from linewidth variation as a function of L_gate), but increased gate length degrades super-V_th performance. (The term δL refers to a 3σ variation in linewidth.) On the other hand, sub-V_th performance is not affected as severely as super-V_th performance, because current can be regained with a small reduction of V_th, with no impact on the I_on/I_off ratio. More significantly, the additional capacitive loading associated with increasing L_gate is significantly smaller for sub-V_th than it is for super-V_th, as shown in Table 3. Sub-V_th operation at longer L_gate values gives the added advantage of a steeper sub-V_th slope. Similar tradeoffs must also be considered with respect to narrow FET channel widths (W). However, the choice of L_gate and W are greatly affected by the circuit application requirements. Gate dimensions have less flexibility in the extreme case in which high performance and high V_dd are at a premium. In this case, the designer can account for the impact of the V_th and slope variations correctly only when predicting sub-V_th and near-V_th circuit behaviors.

Figure 2 Figure 3

Another point to consider is that p-FET and n-FET thresholds can decrease at different rates as V_dd is reduced. This implies that the n–p I_on matching can change drastically, as indicated in Figure 4. Small V_th adjustments can be made to provide the optimal matching for sub-V_th and near-V_th operation; but again, super-V_th operation may deteriorate.

Figure 4

Random channel dopant fluctuation (RDF) is another source of threshold variations that results in FET current mismatch. The 3σ V_th variation (δV_th) induced by RDF is inversely proportional to the square root of the channel area (δV_th ~ A/(W × L)^1/2, where A is a constant of 4 in units of mV × μm, W is the FET channel width in μm, and L is the FET channel length in μm) [2]. Table 4 compares V_th mismatch induced by RDF, across-chip channel-length variations (ACLVs), and across-chip rapid thermal anneal (RTA) variations in a 65-nm technology (L_gate ~ 35 nm). At 65 nm, RDF-induced V_th mismatch is comparable to other sources of V_th variability and will dominate in future technologies as channel areas are scaled down. Although the 30–60 mV of V_th variation has a significant impact on super-V_th matching, a similar variation in the sub-V_th region results in a 2–3x variation in I_on. Some relief from current variation can be gained by increasing FET dimensions, but the reduction is less significant than observed when channels are lengthened to reduce the impact of short-channel effects on V_th variation. One possibly useful approach is to provide feedback, at the circuit level, to FET back-gates or wells in order to match thresholds [3]; however, this adds circuit overhead and is impractical for any circuit that depends on the relative strengths of FETs (i.e., “ratioed circuits”). Nonetheless, back-gate or well feedback may enable lower V_dd in a large design if used only with highly sensitive circuits.

The important lesson is that V_th and sub-V_th slope variations are the key challenges to sub-V_th and near-V_th circuit designs. If a circuit must operate at both high V_dd and very low V_dd (with a strong emphasis on high-voltage operation), minor tradeoffs should be considered, such as lengthening FET channels slightly to reduce V_th variation and making small V_th adjustments to maintain nominal matching between FETs at low V_dd. However, if energy minimization at low V_dd is of paramount importance, significant device optimization studies must be considered. Significant increases in channel length may be advantageous in order to achieve steep sub-V_th slopes and to minimize V_th and sub-V_th slope variations, keeping in mind that channel capacitance plays a smaller role in sub-V_th operation than in super-V_th operation. The use of mid-gap and quarter-gap metal gates in conjunction with the longer channels should be reconsidered [4]. At short channels, mid-gap metal gates can result in poor sub-V_th slopes, but steep slopes can be achieved at longer channels even with low body-doping concentrations. In this case, the V_th is controlled primarily by the metal workfunction and not body doping; hence, V_th variation due to random doping fluctuations is reduced. Furthermore, mobility increases as the doping concentration is reduced. In the future, advanced dual-gate FINFET [4] and back-gated FET [4] structures will become available. Each of these has different benefits for sub-V_th and near-V_th operation. Recent work has shown that dual-gated FETs are ideal sub-V_th devices because they offer the steepest sub-V_th slope [5]. If combined with mid-gap metal gates at long channels, dual-gated FETs may offer sufficient reduction in V_th variations. Back-gated FETs trade off sub-V_th slope for the possibility of further reduction in V_th variations via back-gate feedback. The ultimate choice in device type will depend on how well V_th can be controlled.

FET-channel resistances are very large for sub-V_th and near-V_th operation, providing optimization possibilities in applications in which minimization of energy is the key goal. Because the channel resistances are high, FET series resistance (R_s) and interconnect resistances can be larger without having an impact on performance. For example, the increase in R_s required to reduce super-V_th I_on by 10% is approximately 100 Ω-μm, while a 10% sub-V_th reduction requires an increase in R_s of approximately 6 kΩ-μm. When considering challenges at the FET level, the high R_s values that can occur with the simplest dual-gate process options may not be a concern. Decreasing the gate overlap of source and drain diffusions in order to reduce Miller capacitance at the cost of larger R_s should be considered. Decreasing the dimensions of interconnect is attractive because capacitances can be reduced at the cost of increased resistance. For a net loaded by wire capacitance, this latter tradeoff could be quite significant. A simple sizing suggests that a 1.25x reduction in active power results when a 4x increase in interconnect resistance is accompanied by a 2x reduction in interconnect capacitance. Of course, all of these options compromise performance at high V_dd.

Reliability and susceptibility to wear-out mechanisms in low-V_dd and high-V_dd operation also differ. Hot-carrier degradation is greatly reduced at low V_dd. However, if circuits must operate at both high and low V_dd, degradation during high-V_dd operation can have a large impact on low-V_dd operation. Negative bias temperature instability (NBTI) and channel hot carrier (CHC) effects that cause V_th shifts will be the major concern. Even if circuits operate only at low voltage, where the NBTI effect is greatly reduced, NBTI is made worse by long standby periods. SRAMs, for example, can have very long standby periods and may be susceptible to NBTI even at low voltage. Thus, it is important to evaluate the impact of these reliability effects at low V_dd. On the other hand, electromigration, which increases interconnect resistance, is less of a concern. Susceptibility to radiation needs consideration, and careful analysis of soft-error rates in sub-V_th logic must be conducted.

In summary, the major challenge in sub-V_th FET design is V_th control. In circuits with high V_dd performance requirements, designers must make small compromises to reduce V_th variation and maintain current matching between FETs. However, if energy minimization at low V_dd is the critical goal, significant device optimization studies must be considered. For minimum-energy CMOS, dual-gate FETs show much promise. If combined with low-workfunction metal gates at long channel lengths, dual-gate FETs will help minimize V_th variation and improve sub-V_th slope, the key parameters for sub-V_th operation.

The previous section described significant changes in device-level behavior as supply voltage is lowered toward the sub-V_th regime. In particular, the I_on/I_off ratio is reduced significantly in the sub-V_th region, and devices show an increased sensitivity to the threshold voltage, supply voltage, and sub-V_th slope. At the circuit level, this leads to changes in three areas of concern: noise margins, energy optimality, and sensitivity to process variations. Each of these topics is discussed thoroughly for general CMOS logic, and special consideration is given to the design of SRAM arrays.

Most useful designs have maintained a “safe” difference between the values of supply voltage and threshold voltage to guarantee robustness and performance. However, as designers have known for many years, CMOS is a very robust logic family, and in the absence of variability it is unnecessary to maintain a margin between the supply and threshold voltages to guarantee functionality. The supply voltage of a design can therefore be dramatically lowered to limit the dynamic energy consumed. Once the supply voltage drops below the threshold voltage, current takes the form of weak inversion sub-V_th current, which is modeled by Equation (1). Using sub-V_th current to charge and discharge nodal capacitances, a circuit may function at very low voltages. The theoretical lower limit on voltage scaling was first established in [6, 7] as

(3)

where C_fs is the fast surface state capacitance per area, C_ox is the gate-oxide capacitance per unit area, C_d is the depletion capacitance per unit area, and v_T is the thermal voltage kT/q. The second form of Equation (3) is an approximation of the first assuming an ideal MOSFET (a sub-V_th swing of 60 mV/dec at 300 K) with C_fs ≪ C_ox and C_d ≪ C_ox [6]. An ideal MOSFET can therefore theoretically operate at voltages as low as 36 mV. Sub-V_th swing is generally much higher than 60 mV/dec, so an inverter based on realistic MOSFETs will cease to function at a voltage higher than 36 mV. Furthermore, the result in Equation (3) depends on matching between p-FET and n-FET currents. Proper balancing of pull-up and pull-down networks becomes very difficult when gates have transistor stacks (i.e., series-connected transistors). The relative strengths of the pull-up and pull-down networks are dependent on the values of the inputs to the gate, so the use of stacks raises V_dd,limit well above that of a simple inverter. Table 5 shows simulated V_dd,limit values for several common CMOS gates. V_dd,limit is the lowest voltage for which the voltage transfer characteristic (VTC) has a gain greater than magnitude one when the input voltage V_in equals the output voltage V_out (i.e., |gain| ≥ 1 when V_in = V_out) [6]. Figure 5(a) shows the measured voltage transfer characteristic (VTC) of an inverter at 65 mV with various well biases and confirms that sub-V_th logic functions at room temperature below the previously reported low value of 70 mV [8]. In Figure 5(b), a butterfly curve for a 6T-SRAM cell is shown at a supply voltage of 70 mV, proving that sequential elements also maintain functionality well into the sub-V_th regime. The robustness and energy efficiency of SRAM receives special attention in the subsection below on sub-V_th SRAM design issues.

Figure 5

Voltage scaling is further limited when complex gates are placed in series. Circuit simulation has been conducted to examine the voltage-scaling limits of typical logic using circuit models of an IBM 65-nm PD-SOI process. For this study, we had to redefine V_dd,limit because we were not considering static isolated gates. Here, we define V_dd,limit as the lowest voltage at which an input signal switching event results in a correct output switching event (the switching threshold is defined as 0.5V_dd). All delay values have been normalized with respect to the delays of the respective gates at V_dd = 1.0 V. Table 6 illustrates V_dd,limit for a wire-load-dominated, representative microprocessor critical path. Such critical paths contain long metal interconnects and are interspaced with optimally sized inverting repeaters. Because of the absence of complex static gates (with stacked devices) in this type of critical path, V_dd,limit is very low. As Table 6 shows, this circuit functions properly at supply voltages as low as 60 mV. Table 6 also shows the V_dd,limit for a logic-dominated, representative microprocessor critical path. This path includes a wide variety of gates including NAND3s, AND-OR-INVERT (AOI) gates, inverters, and transmission-gate-based multiplexers. Multiple instances of each of the mentioned static gates are present in this circuit with varying device sizes and p/n ratios. It is important to mention that this circuit does not have any NOR gates and includes parasitic wire capacitances. Because of the presence of stacked n-FETs and p-FETs in various static gates, this circuit fails to operate below 120 mV.

Increasing V_th mismatch between n-FETs and p-FETs further increases V_dd,limit, as is illustrated in Table 7. Two of the entries in the table are labeled “n-FET increase,” and the other two are labeled “p-FET increase,” indicating that the n-FET and p-FET thresholds have been increased by 100 mV. When the n-FET threshold is increased, circuit failure occurs below 200 mV, while when the p-FET threshold is increased, the circuit is operational at values as low as 150 mV. The simulated circuit has large n-FET stacks and no p-FET stacks (because of the presence of NAND3s and the absence of NORs), so a higher-p-FET V_th is more acceptable than a high-n-FET V_th. This explains the lower V_dd,limit for the case in which the p-FET threshold is increased. Although not illustrated in these tables, V_dd,limit is also influenced by the p/n sizing ratios in the various gates of the design.

CMOS is clearly functional at very low voltages. There is a performance price, however, for low-voltage operation. The sensitivity of delay to both supply voltage and threshold voltage in sub-V_th operation has been alluded to in both Section 2 and Tables 6 and 7. Figure 6 shows inverter delay in a 130-nm process as a function of supply voltage. Simulations of the same inverter also show that a threshold shift of only 50 mV results in a 4x change in delay. These general trends become important in discussions of leakage energy and variability later in Section 3.

Figure 6

Unwanted signals, such as noise, must be addressed in any system of logic, particularly in ultralow-power CMOS. For convenience, we partition the problem into two parts, the circuit noise margin and the noise level in the system. In the first part of this section, we compare the quantitative behavior of the noise margin in sub-V_th logic with that of conventional CMOS. We follow this analysis with a view of noise generation in sub-V_th logic, again comparing the behavioral issues to those found for conventional CMOS.

The noise margin is the difference between a valid output logic level and an input level at which the data of a “victim” circuit will be corrupted. (A victim circuit is one that is subject to noise from an external source.) Thus, for a “high” logic level, the high-state margin is given by V_H,margin = V_OH − V_IH, where V_OH is the least positive guaranteed logic output voltage for a valid high state, and V_IH is the least positive input voltage required to disturb the logic state of the receiving circuit [see Figure 5(a)]. V_L,margin is similarly defined, such that a positive value for V_L,margin is sufficient for valid transmission of a “low” logic level. In all following discussions, for convenience we refer to these noise margins in fractional values of the V_dd.

The input levels V_IH and V_IL can be approximated by the unity-gain points of the receiver in question. For this approximation, the relative input levels increase as V_dd is decreased in the extreme sub-V_th region (V_dd < 100 mV) as long as n-FET- and p-FET-drive levels are carefully balanced. Both V_IH and V_IL necessarily approach 0.5V_dd as V_dd is decreased toward the limiting low-voltage limit for bi-stability. Figure 7 shows the increase in (V_dd − V_OH)/V_dd and V_OL/V_dd for a simulated 90-nm-generation CMOS sub-V_th inverter. The reason for the increase is clear; the I_on/I_off ratio is decreasing exponentially with V_dd, roughly as exp(V_dd/mv_T), where m is the “ideality factor,” that is, the subthreshold slope factor described in Section 2. Hence V_OL/V_dd, for example, is expected to increase similarly, as exp(−V_dd/mv_T). The net effect is that the fractional noise margin in sub-V_th logic is fairly constant as V_dd is reduced from a few hundred mV to 100 mV, below which the increasing values of (V_dd − V_OH)/V_dd and V_OL/V_dd result in a decreasing fractional noise margin. Figure 8 illustrates how the fractional output and input levels behave from V_dd = 200 mV to V_dd = 45 mV, where operation becomes unstable.

Figure 7 Figure 8

Noise generation can be approached from a simplified model, shown in Figure 9. Noise is generated by an “offending” path driven by R_driver (R_driver may be thought of as the equivalent impedance of a CMOS output stage) with a load consisting of a path directly to ac ground, and a second path with “bad” coupling capacitance to the input of a victim circuit, which in turn has some “good” input capacitance to ac ground. We refer to coupling capacitance as “bad” because it allows noise from one wire to affect another wire. In contrast, we refer to grounded capacitance as “good” because it helps a wire to resist noise. In addition, the gate of the “victim” is driven by R_good, which, like R_driver, is the equivalent impedance of a CMOS output stage. Typically, the “bad” coupling capacitance arises from adjacent wires that are parallel to each other. To simplify analysis, we consider two limiting cases: 1) R_good is much greater than the impedance of C_good, and 2) R_good is much less than the impedance of C_good.

Figure 9

In the first case, noise generation is effectively given by the ratio 2C_bad/(C_good + C_bad), where the factor of 2 results from a worst-case scenario in which the offending wire and the victim wire switch in opposite directions. This factor of increase is due to the so-called Miller effect. While this ratio is insensitive to the drive characteristics of the transistors, a significant fraction of C_good can be due to gate capacitance to (ac) ground; this gate capacitance is shown to decrease in sub-V_th operation. Thus, in the case in which C_gate may comprise 30% of the total wire load to ground, the noise coupling may increase by as much as 15% in sub-V_th operation. This provides further impetus to customize the interconnect technology toward using narrow, thin wires, providing lower capacitance at the expense of higher interconnect resistance. In particular, noise “scaling” can be preserved, provided that the interconnect capacitances are reduced in proportion to the effective reduction in gate capacitance.

In the second case, in which R_good is much less than the impedance of C_good, the noise coupling is given by (ζC_bad)⁻¹/[R_good + (ζC_bad)⁻¹]. Note that no factor of 2 is needed because R_good can be dominant only in a static case. Here we must consider the scaling of ζ, which is given by the inverse of the characteristic rise or fall time of the offending signal. This rise or fall time is in turn driven by R_driver, which is increasing at the same rate as R_good, and pushes the design into sub-V_th operation. Thus, the noise coupling is expected to be unchanged in this limit. Consequently, sub-V_th noise coupling may actually be smaller than super-V_th noise coupling if sub-V_th interconnect is optimized for lower capacitance and higher resistance.

In conclusion for this section, note that noise margins are largely unchanged in sub-V_th CMOS (to as low as 100 mV), provided that n-FET/p-FET matching can be adequately constrained. This may be non-trivial, particularly in light of stochastic mechanisms such as random dopant fluctuations (RDFs). Below 100 mV, even with perfect matching, the noise margin intrinsically decays until it collapses at the stability limit. Interconnect optimization of capacitance at the expense of resistance is desirable to compensate for reduced gate capacitance as a noise shunt. Otherwise, some extra allowance for noise coupling may be required.

Optimal power and energy analysis
Though absolute noise margins and delay both degrade in the sub-V_th region, CMOS logic continues to function at very low voltages. To justify these delay and robustness penalties, we now consider the power and energy efficiency when operating in the sub-V_th regime. Power consumption has two components: dynamic and leakage. Thus, the expression for power is

P = Pdyn + Pleak,	(4)
P = ½ · Cs · Vdd2 ·  · f + Ileak · Vdd,

where C_s is the switched capacitance of a single inverter, is an activity factor, f is the clock frequency, and I_leak is the leakage current. The “activity factor” is the average number of transitions on a node per clock cycle.

Both dynamic and leakage power benefit from supply-voltage reduction, and dynamic power will continue to improve quadratically as voltage is scaled to the lowest value that guarantees functionality. Circuit designers have traditionally given power more attention than energy, but energy is generally a more suitable metric when battery life is the overriding priority. We therefore begin with a study of energy and show that, unlike power optimization, energy optimization relies upon a compromise between dynamic and leakage energies. Just as in the case for power, energy comprises dynamic and leakage components:

E = Edyn + Eleak,	(5)
E = ½ · Cs · Vdd2 ·  + Ileak · Vdd · tp.

Note that we can safely ignore short-circuit energy in this analysis; the reason is explained below. Typical short-circuit current analysis assumes that direct-path current approaches zero when the supply voltage drops below V_th,n-FET + |V_th,p-FET| because the direct-path current is entirely sub-V_th current below this voltage. Because sub-V_th logic is driven exclusively by sub-V_th current, we redefine short-circuit current as any direct-path current beyond the leakage current present in steady state. A first-order analysis shows that the total short-circuit energy is an approximately quadratic function of V_dd and may be combined with dynamic energy. Assuming a triangular short-circuit current distribution and that Q_sc is short-circuit charge, I_sc is the peak short-circuit current, and t_sc is the total time that short-circuit current exists:

(6)

Note that I_sc and I_on are assumed to scale identically with V_dd, so their dependencies cancel. As a result, Q_sc is linear with V_dd, and short-circuit energy, E_sc = Q_scV_dd, is quadratic with V_dd. Simulations show that the quadratic relation fits very well in the super-V_th region, but in the sub-V_th region, E_sc actually decreases faster than predicted by the quadratic model. This change in behavior in the sub-V_th region is minimal, though, and can be ignored with only a small penalty. If we assume a quadratic dependence on V_dd, E_sc may be modeled using a multiplier in front of dynamic energy because dynamic energy is also quadratically dependent on V_dd. We therefore ignore short-circuit energy without invalidating our analysis.

A critical difference between energy and power exists as illustrated by Equations (4) and (5), namely that leakage energy (per operation) is dependent on circuit delay, t_p. Figure 6 shows that the delay increases rapidly as the supply voltage scales, particularly when the supply approaches the threshold voltage. Even though I_leak [Equation (1)] decreases with supply voltage, the increase in delay is so dramatic that leakage energy quickly overtakes dynamic energy. Figure 10 shows the average power consumption and the energy consumed per operation for a chain of 50 inverters in an industrial 130-nm technology. Here, an “operation” is the work done in a single clock period. In this example, V_dd is scaled, and V_th is fixed at approximately 400 mV. Power decreases monotonically, while energy shows an inflection point caused by the rapid rise in leakage energy. For the circuit under consideration, the energy-optimal point occurs in the sub-V_th region and yields an energy reduction greater than 20x. This result is confirmed by the authors of [9] and [10], who observe sub-V_th voltages to be optimal for an inverter chain and an FIR filter, respectively, with V_th fixed. However, the threshold voltage does not have to be fixed when scaling the supply voltage. The authors of [11] study the energy benefits of simultaneous V_dd and V_th scaling and find that sub-V_th operation is generally more energy-efficient than super-V_th operation when performance requirements are low. Because we are primarily concerned with minimizing energy, we can accept low performance and can take advantage of sub-V_th operation. Given the results of [9–11], we first consider the optimization of circuits in the sub-V_th region. Because a number of applications are expected to have higher energy-optimal supply voltages, we also consider the implications of near-threshold and super-V_th operation. In both cases, the supply voltage is scaled relative to a fixed threshold voltage.

Figure 10

Inverter chain analysis
Simple analysis of an inverter chain helps build an understanding of the balance between dynamic and leakage energies that occurs at the energy-optimal supply voltage. In [9], an inverter chain with n identical stages and an activity factor of is considered. The energy per switching event of this system is given by

(7)

where n is the number of inverter stages, t_p is the delay of a single inverter, I_leak is the leakage current of a single inverter, and all other variables are as previously described for Equation (4). It is clear that sub-V_th operation is optimal for many circuits [9, 10], so this analysis assumes sub-V_th operation. In this analysis, the delay of an inverter with a step input voltage, t_p,step, is modeled using

(8)

This expression is valid for both super-V_th and sub-V_th operation, but in the latter case I_on is modeled using Equation (1). The authors of [9] show that t_p in the sub-V_th region can be approximated as

where η is a technology-dependent parameter that represents delay degradation due to the slope of the input signal. Substituting Equations (8) and (9) into Equation (7) results in the following equation:

(10)

The variables I_leak and I_on both take the form of Equation (1) because we are assuming operation in the sub-V_th regime. Consequently, all terms in the I_leak and I_on expressions cancel except for the exponential V_g dependence, and Equation (10) may be further simplified to

(11)

Equation (11) reveals a great deal about the energy dependencies in the sub-V_th voltage regime. For example, the strong dependence of energy on supply voltage (V_dd) is evident. The quadratic voltage term is initially the dominant term in the expression, but as voltage is reduced far into the sub-V_th regime, the exponential dependence on supply voltage (which reflects circuit delay) begins to dominate. Figure 10(b) illustrates the fact that there is a distinct energy minimum with respect to voltage. We can easily find the supply voltage at the minimum by determining the derivative of Equation (11) and setting it equal to zero. The resulting equation is nonlinear and must be solved using numerical methods. The final expression for the supply voltage at the energy minimum, which we denote V_min, is shown in the following equation:

(12)

V_min does not necessarily correspond to V_dd,limit, described in the subsection on CMOS characteristics at the voltage-scaling limit. In fact, as the subsequent discussion shows, V_min is usually well above V_dd,limit because of the dominance of leakage.

In Equation (12), V_min depends only on the number of device stages, the activity factor, and two process-related parameters, η and m. This simple model has great value because switching between technologies requires only the determination of η and m. The accuracy of the model is confirmed in [9].

The importance of logic depth n and activity factor in Equation (12) is obvious. To understand the relationship between these two parameters, we replace the ratio of n to with a single parameter n_eff. This substitution is valid because logic depth and activity factor affect the energy characteristics of a circuit in very similar ways. A circuit with many stages (large n) will be leaky because the leakage time for each stage is increased. Similarly, a circuit with a low activity factor is more likely to be leakage-dominated because dynamic energy is proportional to the activity factor. In both cases, the circuit will exhibit a higher V_min.

To properly understand the effect of n_eff and V_min on a circuit, it is important to understand the notion of transistor utility [12], which embraces the idea that all transistors in an energy-efficient design should spend as much time as possible doing useful computation because the circuit consumes wasted energy during idle time. We can nominally assume that dynamic energy is a measure of useful computation (because switching transistors consume dynamic energy) and that leakage energy is the penalty paid for idle time. The goal of an energy-efficient design is therefore to optimize the circuit structure such that the ratio of dynamic energy to leakage energy is maximized. Maximizing the dynamic-to-leakage ratio enables a designer to effectively use supply voltage as a “lever” to decrease dynamic energy consumption and consequently total energy consumption. In other words, a design with high transistor utility generally has a lower V_min than a similar design with low transistor utility. In the ideal case, V_min approaches V_dd,limit, the lowest functional voltage.

If we adopt transistor-utility maximization as the goal of a design, it is obvious that a large n_eff is undesirable. Long paths or paths with low activity increase effective idle time and increase V_min. Logic depth and activity factor tend to be a function of high-level architectural decisions, so they may not be characteristics that a circuit designer can easily exploit. However, the circuit designer does have the ability to decrease the penalty for idle time. Leakage-reduction techniques such as multiple-threshold CMOS (MTCMOS) [13], input vector control [14], and threshold control via adaptive body biasing (ABB) [15] are all tools that have the potential to lower V_min and consequently the total energy consumed by the circuit. The leakage problem may also be addressed at the device level by improving the sub-V_th slope. Section 2 pointed to the importance of sub-V_th slope in low-voltage design, and our simple analysis clearly shows that minimizing sub-V_th slope should be a key goal of energy-optimal design.

We now consider whether the previous analysis is valid for a more complex design. Silicon measurements of a simple 8-bit microprocessor with 2-Kb memory in a 130-nm technology are shown in Figure 11. A more detailed description of the architecture may be found in [12]. The form of the curve is identical to that of the inverter chain (thus confirming the validity of the inverter chain analysis), but V_min is higher than that of the inverter chain. The memory, which has a very low activity factor compared with typical logic, is largely responsible for the higher V_min. This example suggests that very low circuit activity could push V_min into the super-V_th regime. The next section investigates this topic.

Figure 11

Energy optimality in the near-V_th and super-V_th regions
As Figure 11 shows, circuit structures with very low activity factors, such as memories, face serious leakage penalties for extremely low-voltage operation. As the leakage energy of a design increases relative to dynamic energy, the optimal supply voltage tends toward higher values. If the threshold voltage is held constant, the optimal supply voltage will likely be near or above the threshold voltage.

We can extend the inverter chain analysis example from the previous section to make some simple but powerful conclusions about operation in the near-V_th and super-V_th regions. Consider an inverter chain with variable activity factor. As the switching activity decreases, the leakage energy of the circuit is unchanged, but the dynamic energy shifts lower. This downward shifting of the dynamic energy curve is illustrated in Figure 12 for a range of values. As the dynamic-energy curve moves relative to the leakage curve, the location of the minimum-energy voltage, V_min, shifts. When V_min approaches the threshold voltage, the leakage-energy curve flattens because delay (and consequently leakage) is less sensitive to supply-voltage changes above the threshold voltage. As a consequence, the energy minimum is flattened, so that the choice of supply voltage can deviate slightly from the optimum with only a small energy penalty.

Figure 12

The core problem, however, remains unchanged. The dynamic- and leakage-energy curves still cross over one another and create an energy minimum. This is a key conclusion that is independent of the region of operation: The location of the energy minimum is entirely determined by the way in which the leakage-energy and dynamic-energy curves interact. Regardless of whether a system operates in the sub-V_th or super-V_th regime, all architectural and circuit techniques such as ABB attempt to shift either the leakage-energy or dynamic-energy curve to improve energy efficiency. Figure 13 shows that V_min behaves similarly over a wide range of n_eff values. Although Equation (12) was derived for the sub-V_th regime, V_min continues to exhibit an approximately logarithmic dependence on n_eff until V_min reaches approximately 600 mV. Above 600 mV, V_min is still roughly logarithmically dependent on n_eff, but the slope of the line becomes steeper. The location of V_min is dependent upon leakage, so the relative insensitivity of leakage to supply voltage in the super-V_th region forces larger changes in V_min in order to reach energy optimality (and consequently the slope is greater). Also note that saturation of V_min occurs at very high n_eff values because dynamic energy becomes insignificant compared with leakage energy regardless of V_dd.

Figure 13

It is clear that the understanding of , n_eff, and transistor utility (described earlier) developed for sub-V_th operation is valuable even when V_min shifts into the near-V_th and super-V_th regions. While the fundamental goal of maximizing transistor utility remains unchanged, circuit design in the near-V_th and super-V_th regions is clearly different from design in the sub-V_th region. Several of the key differences between sub-V_th and super-V_th operation, including delay characteristics and sensitivity to threshold voltage and device mismatch, have already been discussed extensively. In practical applications, circuit design becomes much easier when the supply voltage rises above the threshold voltage. Circuit speeds increase and variability decreases (and noise margins increase in response) as the supply voltage is raised. The real challenge arises when a circuit is optimized so that the energy-optimal supply voltage lies within the uncertain realm of sub-V_th design. The next section shows that one of the most significant challenges is “process-related variability,” a phrase that is clarified in the next section.

Process-related variations, that is, those variations introduced in manufacturing, have become a significant factor that affects circuit performance, even in the super-V_th regime. As a result, there has been a movement to develop methodologies and tools for dealing with variation in order to eliminate the pessimism usually associated with “corner-based” design schemes—those that assign “worst-case” parameter values to determine resistance to variability in order to ensure that the circuit functions properly under a range of conditions. The consequences of process variation are far more severe when voltage is scaled into the sub-V_th regime because of the exponential dependencies of current, and therefore delay, observed in this regime. In addition to the aforementioned relationship between sub-V_th current and threshold voltage, temperature also plays a critical role in determining delay in the sub-V_th regime. The strong dependence on threshold voltage, in particular, leads to wild fluctuations in both delay and energy as well as a considerable reduction in noise margins.

Threshold voltage variations can be broadly placed in two categories: systematic variations (which include lot-to-lot, wafer-to-wafer, die-to-die, and intra-die spatially correlated variations) and random variations. Systematic variations arise from a variety of sources, including gate-length variations, global doping variations, and temperature variations. A number of techniques have been shown to reduce the effects of systematic variation. In [16] and [17], ABB was shown to reduce both frequency and leakage power variations in test circuits. In [18], ABB was used to reduce variation in sub-V_th logic. Dynamic voltage scaling (DVS) is another technique that may be used to limit variation. DVS is traditionally discussed in the context of dynamic power management, but it may also be used to improve both frequency and power yields [17] by enabling post-silicon tuning of the supply voltage. It is likely that adaptive systems that incorporate several circuit techniques such as ABB and DVS will be necessary to achieve high yields in sub-V_th designs.

In addition to systematic variations, random variations (specifically RDF) account for a significant portion of threshold variation [18]. Random variations present a greater threat than systematic variations to delay, power yield, and energy efficiency because global countermeasures such as ABB and DVS cannot be used to effectively address the problem. Researchers have shown that RDF grows in importance as supply voltage is scaled into the sub-V_th regime [19]. Furthermore, as voltage is reduced, total variation grows significantly and becomes dominated by RDF. RDF depends strongly on channel area [2] and may therefore be controlled with careful gate sizing. The effects of RDF may also be reduced by increasing the number of gates in a path because random fluctuations “average out” over long paths. Proper selection of gate sizes and architecture (which determines logic depth) is very important in the design of robust sub-V_th circuits.

In the subsection on finding the energy minimum, we showed that energy minimization relies on the proper balance of dynamic energy and leakage energy. The strong threshold dependence of leakage makes energy optimization strongly dependent on variability. Researchers have developed statistical models of circuit delay, power, and energy and have shown that variability raises V_min by as much as 78 mV and is therefore a threat to energy efficiency [19]. The net voltage and energy shifts are in the positive direction because delay has a lognormal distribution if we assume a normal threshold-voltage distribution. A distribution of delays across many designs is therefore skewed toward longer delays. This effective increase in delay raises the relative importance of leakage, which increases the V_min and the total energy of a design. Larger gates and longer logic paths provide the simplest and most powerful solutions to RDF, but these are, in general, contradictory to the goals of energy minimization. Upsizing increases dynamic energy, while larger logic depths lead to lower transistor utility. Designers must therefore carefully strike a compromise between the minimization of variability and the minimization of worst-case energy.

Although energy efficiency is a serious question in the face of variability, robustness is a more pressing concern. Even a small mismatch between p-FET and n-FET threshold voltages (introduced by either systematic or random variations) causes skewed current ratios and a dramatic reduction in noise margins. Table 7 shows how a systematic threshold mismatch can lead to a considerable increase in V_dd,limit. We must also consider how noise margins are affected when the supply voltage is greater than V_dd,limit. Simulations of an inverter (130-nm-technology node) with V_dd = 200 mV show that noise margins are reduced by 19%, 38%, and 79% given p-FET/n-FET threshold mismatches of 25 mV, 50 mV, and 100 mV, respectively (where a mismatch of 2δ means |V_th,p-FET| = |V_{th,p-FET,nominal}| − δ and V_th,n-FET = V_{th,n-FET,nominal} + δ). These reductions are clearly not tolerable, and hence significant effort to control threshold matching is necessary. Static noise margins are of particular importance in SRAM, implying that designers of sub-V_th memories must pay special attention to mismatch problems. SRAM design issues are covered in detail in the next section.

Process-related variability is one of the critical barriers that must be overcome for sub-V_th logic to have widespread industrial use. A combination of global techniques including ABB and DVS should be employed in combination with careful selection of design parameters, including logic depth and transistor sizing. Well-designed logic, which accounts for variability from the beginning of the design cycle, fosters high circuit yields while also minimizing energy.

The complications of sub-V_th design have been covered extensively for typical logic. We now make special considerations for SRAM. As a result of reduced activity factors, energy consumption due to leakage is especially important in SRAM caches. Depending on the size of the memory, only a small portion may be active at any given time. As shown in Figure 12, such a condition inevitably increases V_min because reduced dynamic energy shifts the overall energy minimum. This suggests that for ultralow-power designs, SRAM arrays should be operated at a higher supply voltage than that for logic. Figure 14(a) demonstrates this basic concept for a 65-nm process, where the supply voltage that minimizes energy is above 0.4 V because of a low activity factor. With progressively higher levels in the memory hierarchy that are larger or even lower in the activity factor, V_min will increase further.

Figure 14

In an SRAM cell, a proper ratio of device strengths must be maintained among the pass-gate, pull-down, and pull-up transistors to ensure functionality under write, read, and standby conditions. When the supply voltage is reduced, acceptable ratios must be maintained: The drive strength of the pass-gate must be greater than that of the pull-up transistor to allow writing of the cell, and the pull-down must be stronger than the pass-gate to avoid accidental flipping of the cell during a read event. In the standby mode, functionality constraints are the same for logic: The two inverter transfer characteristics must be maintained. In general, the read and write requirements provide more severe constraints on cell functionality at low supply voltages. With proper setting of device threshold voltages and widths, however, cell functionality can be maintained even  at extremely low voltages. Measurements  of a  6T-SRAM cell shown  in Figure 5(b) confirm that bi-stable operation is possible with V_dd as low as 70 mV. In such a case, V_dd,limit can be lower than V_min, and optimum energy can be achieved.

The rapid increase in random process-related variability in recent technology generations, especially variability due to random dopant fluctuations, can have a severe impact on V_dd,limit for complete SRAM arrays. Such variability is particularly important in SRAM because of the widespread use of minimum-size devices and aggressive technology ground rules. While a single cell with perfectly matched devices can function at very low voltages, from a statistical standpoint, cells with significant threshold-voltage mismatch will exist in a large array. Such threshold-voltage variation can effectively degrade noise margins such that cell functionality is compromised [20, 21]. When variability is considered, V_dd,limit rises dramatically for a complete SRAM array. As an example, Figure 14(a) shows that the variability characteristic of a 5σ cell (as needed to yield an ~1-Mb cache under random variation) increases V_dd,limit to well beyond V_min for a 65-nm technology. In addition, this increase is expected to become more serious as technology scales [22]. As such, optimal energy consumption cannot be achieved because an SRAM array cannot function at the optimal voltage for energy consumption under the presence of variability.

Error-correction codes and redundancy are often used to address variability in today's SRAM arrays, but these techniques will most likely be insufficient to completely address the widespread problems expected at low voltages. New circuit techniques must also be used to counter variability. By modifying the traditional 6T-SRAM cell circuit, a more variation-tolerant design can be attained. With the 8T cell, as depicted in Figure 15(b), significantly improved read noise margins can be realized [23]. This improvement occurs because the read-disturb condition [as depicted in Figure 15(a), in which the stored “0” node of the cell is pulled above ground] is eliminated by the introduction of a separate read port in the SRAM cell. With discrete read and write ports in the cell, the device ratio constraints of the traditional 6T-SRAM cell for read and write functionality are removed, which allows for simultaneous improvement of both read and write noise margins. As a result, variability tolerance is greatly enhanced, and V_dd,limit can be reduced to less than V_min. As shown in Figure 14(b), employment of an 8T-SRAM design can allow for operation at the supply voltage for optimal energy, thus making it a desirable design option for ultralow-power SRAM caches.

Figure 15

Power-aware microarchitectures are able to have a substantial impact on power consumption, and can be more valuable than transistor-level remedies in reducing total power. This section covers several techniques that may be used to shift V_min and tune energy efficiency at the architectural level. The role of multi-core processing in recovering some of the speed penalty paid for sub-V_th operation is also discussed in this section. In order to understand the value of energy-efficient architectural techniques, we first discuss several metrics that are commonly used to describe energy and power efficiency.

Common architecture metrics capture the influence of energy minimization design for chip logic. Energy- and power-driven design affects area and performance as well as power; capturing these influences in selected benchmark conventions becomes important. Below, we describe selected common benchmarks that provide insight into energy use.

• MIPS per watt: The number of instructions completed by a processor is often described by the millions of instructions per second (“MIPS”) completed at peak load. This benchmark, divided by the power consumption (in watts), describes the power cost of an architecture throughput technique. More effective power- and energy-aware architectures exhibit higher values of MIPS per watt. Supplemental logic circuitry is typically added in high-performance microprocessors to architecturally improve throughput. These performance accelerators add more circuits to execute the same logic and reduce power efficiency. Thus, the total energy cost of an instruction rises as these innovations are added.

• Energy–delay product (EDP): For a given benchmark logic path, the product of the path delay and its total ac and dc energy consumption provides a measure of the effectiveness of the architecture. Large relative values of EDP indicate increased delays and/or high energy consumption, neither of which is tolerable in a power-constrained machine. EDP is often computed for common benchmarks such as a ring oscillator comprising the inverter driving a fan-out of four additional inverters (“INVFO4”). The utility value of EDP is realized when evaluating the design “return” as a result of accepting reduced performance. Active and static power per INVOF4 is often quoted in the literature [24].

• Transactions per CPU cycle (TPCC): Energy-reduction techniques often have a negative impact on microprocessor throughput; for this reason, the designer must consider changes to the number of transactions per CPU cycle (“TPCC”) that can be retired. TPCC is a measure of microprocessor logic efficacy and is purely an architecture performance metric. Nonetheless, TPCC is a superb bellwether that the system designer can use to assess overall system impacts to power management.

Each of these metrics offers valuable information to the designer. However, no single metric is best for all applications. Instead, designers must be careful to choose the metric that best describes the particular power, area, and delay requirements of an application. Though different applications may be driven by different metrics, the applications will use very similar energy-reduction techniques. The following two subsections describe some of these architectural techniques.

Semitransparent uniprocessor power-management techniques reduce power through consideration of under-utilized resources. Note that we use the term semitransparent to refer to a technique that is managed at the hardware level and that does not require support from the operating system. Adaptive body biasing, or ABB, modulates the voltage of the substrate in order to dynamically change the static-power-vs.-active-performance tradeoff asserted by threshold voltage. This technique was mentioned in Section 3 as a tool that may be used to limit systematic threshold variability in a sub-V_th system. In ABB, machine state requirements are anticipated via instruction-lookahead techniques, and substrate voltages are adjusted to optimize power without dramatically affecting performance [16]. The use of ABB in the super-V_th regime has recently fallen out of favor. In [25], it was shown that the application of a reverse body bias (RBB) becomes less effective with technology scaling. Short-channel effects (SCEs) worsen with shrinking transistor dimensions, so threshold control via ABB becomes less effective. In the sub-V_th regime, this problem is much less severe because SCEs, in particular DIBL, are much reduced. It is important to note that ABB is in accordance with the energy model derived in Section 3. By reducing the standby-mode leakage, ABB lowers the penalty paid for idle time, raises transistor utility, and lowers V_min.

Alternatively, logic may be partitioned for placement in specific voltage islands with independent supplies that are compiler-controlled [26]. In Section 3, it was observed that different circuit blocks tend toward different energy-optimal supply voltages. Voltage islands are attractive because they enable a designer to target the energy-optimal conditions on a block-by-block basis rather than on a system level. Memory, in particular, is expected to have a much higher V_min than conventional logic. With memory and logic on different voltage islands, memory would be able to operate at higher voltages to address both functionality and leakage problems, and logic would be allowed to scale voltage more aggressively to yield lower dynamic energy.

Just as different blocks have different V_min values, different runtime conditions (such activity factor and temperature) may require the scaling of supply voltages to maintain energy optimality. Fine-grained dynamic voltage scaling (DVS) allows tuning of a design for runtime conditions and therefore holds promise for use in dedicated energy-optimal design. DVS may also be used to achieve combined performance and energy targets [27]. In [28], DVS was used in combination with ABB to effectively minimize power under a performance constraint, and the system was found to be functional at voltage levels as low as 175 mV. Such an architecture has the potential to target energy optimality given both variable runtime conditions and process variations. A DVS system that operates in both sub-V_th and super-V_th regions requires careful design because, as we saw in Section 2, n-FET/p-FET mismatch is a function of supply voltage.

Voltage gating, or multiple-threshold CMOS (MTCMOS), is yet another power-management technique in which large on-board header and footer MOSFETs provide power to specific domains of the microprocessor chip. When the resource in these domains is no longer needed, their supply access is cut by these devices [29</