Optimizing CMOS technology for maximum performance

For the past several decades, the semiconductor industry has relied on a progression of smaller, denser, faster, cheaper MOSFETs to provide increasingly better products for digital electronics. This process of shrinking CMOS transistors in order to attain these improvements is known as scaling, and its progress is often characterized by measuring the device speed. As CMOS scaling continues, however, it is increasingly important to analyze potential technology design points for their impact on overall chip performance, and not just for their impact on device speed, because chip-level power constraints as well as device and process variability can seriously diminish the value of device innovations. The high cost of developing new technology options also makes it vital to gain an early understanding of their potential benefit to the final products, so that developments with little benefit can be avoided. This paper describes a high-level technology optimization tool, and the results of using it to perform chip-level analyses of potential technology options for the 45-nm and 32-nm generations. These options include enhanced mobility, high-permittivity gate-insulating materials (“high-k”), metal gate workfunctions, and thermal solutions.

Most prior work in this area has focused on system-level power and performance estimation for extrapolating the behavior of future technologies, using estimated critical paths and fairly detailed system descriptions to determine clock frequency, often with much attention paid to the nature and use of the wiring hierarchy. Early examples of prior work are described in [1–3]. Second-generation modeling systems have included GENESYS [4, 5], RIPE [6], BACPAC [7], and, more recently, GTX [8]. Although some of these models are quite detailed at the system level, and optimize various aspects of the wiring and its usage, they have not generally sought to optimize the device technology, preferring to treat information on device technology as a user input. J. D. Meindl et al. have performed a system-level analysis of the limits to scaling for both devices and wires, looking at limits that are caused by a wide range of physical effects [9]. Threshold- and supply-voltage optimization has frequently been studied as a means to reduce power dissipation (see for example [10, 11]), while other work has focused on minimizing power for a fixed performance, subject to various constraints [5, 12, 13]. Recently it has been argued [14, 15] that power should be considered as the primary constraint that determines how far technology can scale, and that the different power requirements associated with different applications result in different limits to scaling. These prior studies formed the basis for an interdisciplinary CMOS design space study [16], in which many aspects of CMOS design were combined into a single model for optimizing CMOS device and wiring technology, with an emphasis on new device scaling aspects.

The work described in this paper builds on the previous design space studies by adding an improved, calibrated device model, accounting for on-chip tolerance issues, accurately capturing the area and power allocations of real processor chips, and implementing detailed temperature dependences and heat-sink models. This tool is believed to provide the best available analysis of the relative utility of proposed technology options because it attempts to “self-consistently” optimize the devices themselves.

The next section describes the overall optimization approach, followed by an explanation of some of the details of the models. Results of the optimizations are discussed.

If Moore's law [17] could provide a path for unbounded progress, as some projections have implied, our goal of seeking an optimum CMOS technology would not be meaningful. The reality, however, is that CMOS technology is bounded. The existence of an optimum technology is illustrated schematically in Figure 1. When device dimensions are large and threshold voltages are high (at the left side of the curves), dissipation caused by leakage currents can be low. The shrinking of dimensions reduces capacitance and enables increasing performance at fixed power. However, device scaling eventually leads to increasing leakage current, due to quantum-mechanical tunneling and subthreshold current. When the total power is constrained, this leakage dissipation ultimately dominates the power consumption, leaving very little power left over for active circuit switching, which leads to a loss of overall performance beyond some point in the scaling process, even though the devices may be getting faster (the right side of the curves). The height and position of the maximum performance-versus-scaling curve depends on the power constraint and other system conditions, but a maximum does exist. This performance-versus-scaling situation applies to cases in which the power constraint is associated with a roughly fixed degree of architectural complexity. This argument for the existence of an optimum should generally apply to all computational electronics, because it depends only on some very broad features of device physics: 1) electrostatics imposes geometric constraints on the relative device dimensions; 2) thermodynamics imposes constraints on voltage reduction; 3) quantum-mechanical tunneling effects inevitably cause exponentially increasing leakage currents when dimensions are sufficiently reduced; and 4) various practical considerations limit power dissipation.

Figure 1

An optimization tool has been developed to determine the technology parameters that lead to this optimum performance for CMOS technology. The program involves a collection of models that span the material, device, circuit, and system levels, some aspects of which are described in more detail below [9, 16]. The overall structure of the optimization tool is shown schematically in Figure 2. The goal is to find the values of the device technology parameters that will result in the greatest possible processor performance for a given power level. We have chosen to measure performance in terms of a total logic net transition rate, LTR. This is the total number of state changes per second for all of the logic nets in the processor core(s) combined. We have deliberately chosen this metric, rather than a critical path-delay metric, because it allows a substantial degree of independence from the architectural details, making our results more generally useful for changing architectures. This metric relies on the expectation that the rate at which useful instructions can be executed by the processor will monotonically increase with LTR. An alternate optimization metric also was considered in [16], based on total computation received per dollar spent (on both chip and energy) over the expected life of the chip. Because it was shown in [16] that both optimization approaches give similar results, we have focused on maximizing LTR at fixed power in this paper.

Figure 2

As in [16], to reduce complexity and narrow our focus, only the logic devices in the processor core are actually optimized; it is assumed that the power and speed of the clock and latch circuits, registers, memories, and I/O can ultimately all be optimized with essentially the same power/performance result as the logic part of the processor. To achieve accurate results at the chip level, we can use actual chip data to set the processor core complexity, and use the fraction of the chip area and power that is used for logic. The optimization controls the actual size of the chip, and hence the power density, by adjusting the device and wire sizes.

Because memory actually occupies the majority of the chip in modern processors, it may seem unreasonable not to include it in the optimizations. However, we have not done so because of the previously mentioned observation that different applications must be separately optimized [14]. Memory has very different requirements than logic, which lead to optima that are quite different from those for logic. The best system performance can certainly be obtained by creating a technology that offers different, separately optimized devices (and voltages) for memory and for logic. If economic considerations force memory and logic to use the same devices, optimization across both sets of requirements might very well find different results than those reported here, which are for logic by itself.

The basic optimization methodology starts with definitions for power and delay as functions of the underlying technology parameters. In an inner programming loop, one degree of freedom (usually the supply voltage, V_DD) is used to satisfy the power constraint, and then in the outer loop, the remaining variables are optimized to find the maximum possible performance.

The total power (P_TOT) calculation includes dynamic switching power (P_DYN), power due to subthreshold leakage current (P_subVT), power due to gate oxide tunneling current (P_ox), and power due to drain-to-body tunneling current (P_B2B), as defined in the following equations:

(2)

PsubVT = 1.7βIoff · NCKT · VDD · W · Joff(VT, VDD, tox, η, LCH),

(3)

Pox = NCKT · FI · VDD · LG · W · Jox(VT, VDD, tox, η),

(4)

PB2B = NCKT · FI · VDD · LG /2 · W · JB2B(FMax, VDD),

(5)

where V_DD, V_H, V_L, and V_T are the supply voltage, high-logic-level, low-logic-level, and threshold voltage, respectively, and is the average switching delay of a loaded logic stage (a NAND gate, with average fan-in, FI, usually set to 2 and average fan-out of 1.65). N_CKT is the number of logic gates, C is the average total load capacitance, _S is the switching activity factor, ℓ_D is the logic depth, J_off is off-current density (at V_L) of a typical logic FET (see next section), J_ox is the oxide tunneling current density (at V_H) [15], and J_B2B is the band-to-band tunneling current density from drain to body (at V_H, and using junction area ½L_GW)) [15, 18]. t_ox is the oxide thickness, η is the subthreshold ideality, W is the average FET width, L_G and L_CH are the gate length and channel length, F_Max is the peak field in the body–drain junction, which depends on the doping and the voltage, and β and β_Ioff are tolerance-related correction factors. The power contributions are separately computed for logic and for the buffers that are placed in long wires (i.e., repeaters).

The performance metric, LTR, is computed from the delay as

(6)

where CPI_eff is a correction factor to take into account the impact of long wires and their repeaters, described in a later section. The loaded logic delay computation proceeds in steps as in [5]. First, the basic device delay is computed using a modified CV/I form that has been shown to accurately take into account output conductance effects [19]:

(7)

where I_eff = ½[I_DS(V_DD, ½V_DD) + I_DS(½V_DD, V_DD)], the Cs are average capacitances, as indicated by their subscripts, and I_DS(V_DS, V_GS) is drain current as a function of drain and gate voltages, which is described in the next section. Next, the wire RC and time-of-flight delays are computed, and combined using an empirical formula [3, 5]:

(8)

3 = Lwire /(c/2),

(9)

4 = (24/3 + 34/3)3/4,

(10)

where R_wire is the temperature-dependent wire resistance, L_wire is the average wire length, and c is the speed of light. Finally, these delays are combined and divided by a rise-time correction factor due to Sakurai and Newton [19]:

(11)

where is the power-law exponent described in the next section.

The structural portion of the device model assumes bulk or partially depleted silicon-on-insulator (PD-SOI) FETs, and uses the effective doping, N_eff, in conjunction with a first-order analytic 2D Poisson solution to determine V_T, η, and DIBL (drain-induced barrier lowering). This model yields continuous, physically realistic device characteristics for all gate lengths, from punch-through to long-channel. Because the Poisson solution depends on L_CH, gate insulator thickness and material, and body doping, we have fully captured the underlying technology dependencies in a very general way. The current–voltage model is a generalization of Sakurai's alpha power-law model [19], in which we use the Fermi–Dirac function F₋₁ to achieve a smooth transition between an power law above V_T and an appropriate subthreshold exponential tail so that the same model can be used for both ON and OFF currents. The intrinsic saturation current is given by

(12)

where V_GS is the gate-to-source voltage, _I is the gate insulator permittivity, and t_ox^eff is the effective thickness of the gate insulator, including quantum effects and poly-Si depletion. e is the electronic charge, E_C is the characteristic field in the velocity–field relationship, μ₀ is a calibration parameter with units of mobility, β and s are exponents fitted to available data, μ(E_⊥,T) is the universal mobility curve [20] as a function of the effective perpendicular field and the temperature, and μ_x is a mobility enhancement factor used to account for technologies that improve mobility. V_DS dependence is accommodated by means of a DIBL adjustment to V_T. Source and drain resistance, R_CS, is included by using a numerical iteration to self-consistently adjust V_GS and V_DS to account for the extrinsic voltage drops. Table 1 gives the values used for the constant-valued parameters.

Table 1 Values for various constant model parameters.

Description Symbol Value Activity factor over logic depth S /ℓD 0.012 I–V curve power law 1.462 I–V formula gate-length exponent β 0.405 I–V formula mobility exponent s 0.430 Mobility calibration parameter μ0 132.3 cm2/V-s Critical field EC 2.5 × 104 V/cm Halo exponent 1 n1 −0.574 Halo exponent 2 n2 2.18 Maximum logic depth ℓDmx 10 Number of logic stages in typical instruction nLI 60 Latency penalty weighting factor 0.1

Halo doping is a fabrication process in which body dopants are implanted at angles from both the source and drain side of a FET. This is very useful because it causes the effective doping, N_eff, in the channel of a MOSFET to increase when the gate length becomes shorter, which tends to compensate for the electrostatic short-channel effects. This is accounted for in our model through the fitting function

(13)

where N_D sets the doping magnitude, n₁ and n₂ are fitting exponents, and the parameter x_e sets the channel length scale over which N_eff varies. x_e should be related to the characteristic length scale of the halo-doping profile. This is one of the parameters that must improve from generation to generation in order for scaling to proceed. The source/drain doping usually causes overlap between the gate and the source and drain, so the channel length is offset from the gate length (L_CH = L_G − x_ovlp) by an overlap distance, x_ovlp, that must also decrease as technology improves.

The model is calibrated to 2D drift/diffusion FIELDAY (FInite ELement Device Analysis) [21] simulations at several technology nodes, as shown in Figure 3. The correlation between full 2D device simulations and our simple compact model is excellent, considering that only 14 fitting parameters are used to match this entire set of data, which includes three different gate lengths at both the 90-nm and 45-nm technology nodes. The values of most of these parameters are included in Tables 1 and 2.

Figure 3

On the basis of fits to FIELDAY simulations and ITRS roadmap considerations, the set of adjustable parameters for the FET model were chosen for each technology node, as shown in Table 2.¹

Table 2 Fixed technology parameters that vary by node.

Description Symbol Technology node (nm) 130 90 65 45 32 Wire 1/2 pitch (nm) 175 120 90 70 50   Gate overlap (nm) xovlp 19 8.74 3 −1.03 −1.5   Halo scale length (nm) xe 61.5 53.4 46.3 40.2 34.9   Contact resistance (Ω-cm) RCS 0.0129 0.0136 0.0144 0.0152 0.0161   LER sigma LG @W = 1 μm (nm) 0.28 0.28 0.28 0.28 0.28   ACLV (nm) 3.9 2.7 1.8 1.3 1   Mobility enhancement factor μx 1 1.4 1.7 2 2   Gate depletion (nm) 0.4 0.4 0.3 0.3 0.01   Wiring permittivity kwiring 3.9 3.5 3.2 2.8 2.5   Permittivity (gate insulator) I 4.7 (oxynitride) 4.7 (oxynitride) 4.7 (oxynitride) 4.7 (oxynitride) 20 (HfO2)

The following within-chip tolerances are included in the analysis: discrete dopant V_T variation, random gate-length variation due to line-edge roughness (LER), across-chip gate-length variation (ACLV), V_DD variations, and signal coupling noise. The model estimates the impact of these variations on the average subthreshold leakage current and on the worst-case delay. It also checks that 6σ V_T and noise shifts do not cause an individual NAND gate to fail, although this is not usually a problem.

The impact on subthreshold leakage current is estimated by observing that the doping variations, gate-length variations, and noise combine to create an approximately Gaussian distribution, ρ, of equivalent threshold voltage with sigma, σ_VTeff. When this Gaussian distribution is integrated against the exponential off-current dependence, it yields an average shift [14]:

(14)

Thus, the background leakage current increases by the factor

(15)

and so does the static power dissipation. If σ_VTeff exceeds kT, this factor can become quite large.

The impact of random variations on worst-case delay is estimated on the basis of the following analysis. Each path i in the set of all paths has a distribution ρ_i(t) of worst-case delays, where “worst case” means the longest possible delay that can occur due to any conceivable instruction sequence (i.e., due to worst-case signal coupling and supply noise). The distribution is over random intrinsic device variations (e.g., variations in V_T). The distribution should also include across-chip variation. Across-chip variations probably have correlations, but to a first approximation we may treat them as independently random and consider them as part of the intrinsic variations.

Thus, the probability of path i failing (by taking too long because its delay is longer than the clock time) is qi = tCKρi(t)dt, where tCK is the desired clock delay. Then, the yield for the whole chip is Y = Π (1 − qi), where the product is over all independent paths. Each path is considered as a set of stages, so that i = ∑j = 1ni ij, summing over the ni stages of the ith path. Next, approximate ij as 0, the nominal value of the delay, and assume that the distribution of ij is Gaussian and can be characterized by a σ that can be estimated numerically by using a worst-case vector of variations away from the nominal case. Then, set i = ni0 and σi = (ni)σ. Now,

(16)

where

Next, treat n_i as a continuous variable, and let P(n) be the density of effectively independent paths. Then,

(17)

where ℓ_Dmx is the maximum logic depth. If the P(n) density function can be treated as trapezoidal, then to first order only the value at ℓ_Dmx matters, and Equation (16) may be approximately evaluated as

(18)

This equation gives yield Y as a function of t_CK, which is implicitly present in u.

Since we are given Y and want to find t_CK, we can numerically reverse this equation and solve for t_CK by iteration. Normalizing by ℓ_Dmx0, which is the nominal value, gives

β = tCK /ℓDmx0.

(19)

Figure 4 shows contours of constant β for a range of σ/₀ and yield. The value of P(ℓ_Dmx) is not well known, but fortunately β has only a weak logarithmic dependence on this parameter. Our calculations use P(ℓ_Dmx) = 0.125N_CKT.

Figure 4

As noted before, to reduce complexity, only the logic devices and repeaters in the processor core are actually optimized; we assume that the power and speed of the clock and latch circuits, registers, memories, and I/O will be separately optimized and that the power/performance result of doing so will be essentially the same as for the logic part of the processor (although the optimal devices will be different). The assumed packing density of logic transistors has been adjusted to reflect actual design practices, as have the power allocations. On the basis of analyses of 90-nm- and 65-nm-generation IBM processor chips, we have assumed that 33% of core power and 15% of core area is associated with logic. For this purpose, “logic” excludes latches, clock buffers, registers, and all other forms of RAM. Depending on the processor chip configurations being simulated, we have assumed that 50–75% of the chip power is dissipated in the cores and that 50–75% of the chip area is devoted to cache.

Rent's rule [22] is used to determine average wire length for shorter wires. Repeaters are placed in long wires, with the average repeater width and separation being optimized as part of the overall optimization. In addition, we assume that wires with repeaters are on higher levels of the wiring hierarchy and are two times the size of the regular wires, thus lowering their resistance. This is a very simplified approximation to the detailed optimization of the wiring hierarchy that has been pursued by some [13], but we believe that it is sufficient for addressing the underlying device technology optimization in which we are interested. Furthermore, rather than independently optimizing the repeaters on individual wires [5], which raises questions of which sort of optimization to perform, we have chosen to merge the repeater optimization into that of the whole chip. The impact of the long wires on overall performance is captured in a latency-oriented model described in [16]. The model is based on the observation that long wire delay does not directly influence cycle time when designing a new processor, because it can be absorbed in increased pipelining, but the latency of long wires does contribute to the inefficiency of the processor by increasing the effective CPI (cycles per instruction) due to “instruction misses” (times when the processor must wait for a previous instruction to finish before launching a new instruction because the processor needs the previous result). To account for this latency, an application-dependent latency penalty factor is introduced, and an effective CPI (associated with latency issues only) is computed as a weighted average between the case in which instructions can be launched immediately (CPI = 1) and the case in which the previous instructions must finish first:

(20)

where _cycle = ℓ_Dmx is the cycle time, and _instr = n_LI + n_RIR is the total time required to complete a typical instruction, from beginning to end, including all the stages of logic (n_LI) and the transmission time for long wires, which depends on the repeater stage delay, _R. This penalty factor enables the repeater characteristics to be included in the optimizations. The number of repeaters in a typical instruction is taken to be n_RI = 2(A_core)/S_R, where S_R is the average spacing between repeaters, and 2(A_core) means that the total wire length requiring repeaters is twice the edge of the processor core. We usually set  = 0.1.

A thermal model has been implemented that allows the junction temperature to be self-consistently determined from the power dissipation. Temperature dependence is included in the subthreshold leakage current, the mobility model, and the wire resistance model. The heat-sink model is illustrated in Figure 5, and can accommodate hot spots, 2D and 3D thermal spreading resistance, and a wide range of materials.

Figure 5

Junction temperature constraints can also be imposed on the optimizations, to reflect realistic reliability concerns. At low power levels, when the junction temperature does not reach the constraint value, there is no effect, but at high power levels, when the temperature would exceed the constraint value, the chip area is increased by the addition of non-dissipating, unused areas. This increase in area reduces the power density just enough to keep the temperature at the constraint value. Such design points are undesirable, but represent the best that could be done if one insisted on dissipating excessive power.

Figure 6 shows the detailed results of optimizations for the 90-nm to 32-nm-technology nodes, using the node characteristics shown in Table 2. These optimizations are performed for a dual-core processor chip with aggressive air cooling. Seven variables have been optimized: gate length, oxide thickness, halo doping, mean width, mean repeater spacing, mean repeater width, and V_DD. The peak in performance versus power seen in Figure 6(a) occurs because the heat-sink technology is fixed and the temperature rise is constrained. The peak corresponds to the power at which the maximum temperature is first reached, as can be seen from the constant temperature contours in the figure. In this case, the maximum temperature rise is 60°C. The only way to increase power further, without increasing temperature, is to spread the chip out, as described in the previous section. This lengthens wires and slows down the chip even though the power level is higher. Design points at power levels beyond the peak are undesirable and should be avoided in practice. Low-power designs require larger, less scaled devices [Figures 6(b), 6(c)] in order to reduce leakage currents, indicating that only the highest-power applications can utilize extremely scaled devices. Figure 7 shows the optimal allocation of power dissipation among the various mechanisms for a processor using water cooling (which allows higher power dissipation), from which it can be seen that gate leakage dissipation should not exceed a few percent, but optimal subthreshold leakage can exceed 50% for very high-power designs.

Figure 6 Figure 7

In an effort to understand the accuracy of our calculations, we have checked to see how our model predictions for past technology generations compare with what was actually built. We have found that the gate lengths [e.g., Figure 6(b)] agree reasonably well at the power levels for which technology generations have been targeted, but our supply and threshold voltages tend to be lower than what was used in practice, rising only slowly as the lithographic dimension increases. Two main reasons exist for this voltage discrepancy: 1) We have not yet included process variations in our analysis, which would undoubtedly slightly increase our optimized voltages; and 2) voltages used in past designs were probably not optimal. Ten to fifteen years ago, supply voltages were determined by external considerations, such as the “industry standard” five-volt power supply, and there was much resistance to the idea of lowering voltages, even when it became clear that reliability concerns demanded a change [23]. Furthermore, technologists tended to think that standby power should be quite low (unlike the optimized results in Figure 7), which required higher V_T, and commensurately higher V_DD. Consequently, we believe that past technology generations had non-optimally high voltages, making our comparison partially unsuccessful. On the basis of comparisons with more recent technologies, we expect our modeling to accurately predict trends, but exact optimum values for a specific scenario may be less accurate than the trend predictions because of the many simplifying assumptions.

Next we consider future technology options. Metal gates are simulated by removing the poly-Si depletion effects and adjusting the workfunction. High-k gate stacks are simulated using a double-layer bandgap-dependent tunneling model. As can be seen in Figure 8, high-k combined with metal-gate can potentially yield excellent chip-level performance enhancement, as is also seen in the 32-nm node in Figure 6(a), but metal gates by themselves do not offer much benefit over poly-Si, even for workfunctions that are equivalent to poly-Si. As the workfunction shifts from band edge toward midgap, a significant loss of performance occurs for both metal-gate and high-k combined with metal-gate. This loss occurs because the optimizations compensate for midgap workfunctions by lower doping (which increases depletion depth) and by raising the supply voltage (which necessitates thicker oxide). According to these optimizations, the benefits of the use of high-k are lost for PD-SOI by the time the workfunction reaches quarter-gap.

Figure 8

Many future technology options involve increasing mobility, such as the use of strain, hybrid-orientation substrates, and SiGe layers. Figure 9 shows that mobility increases can indeed increase chip performance, though with diminishing returns for large increases in mobility. This performance increase is larger for high-power chip designs than for low-power designs. It is not yet clear, however, how much mobility improvement will be possible at 32 nm, because much of the available increase will already have been achieved in previous nodes.

Figure 9

If we pessimistically suppose that some improvements will not be manufacturable, we obtain the results shown in Figure 10. Figure 10(a) serves as a baseline, in which improvements are successfully implemented according to Table 2. This is the same data as for Figure 6(a), on a linear scale, and we have added a high-k option for the 45-nm node, which clearly illustrates the potential benefits of an optimal high-k solution. Figure 10(b) shows the results if we are unable to improve the wiring dielectric constant and it remains fixed at 2.8. This reduces the peak performance of the 32-nm generation to the same value as for the 45-nm node. Finally, in Figure 10(c) we assume that the device technology is also fixed, with L_G = 36 nm, t_ox = 1.1 nm, and the wiring dielectric constant k_wiring = 2.8. In this case, the generation-to-generation changes involve only the packing density, as driven by the widths and wiring pitch, which are not fixed. A significant peak performance loss occurs in future generations, with very little gain even at low power, making it clear that density improvements alone are insufficient for future technology generations.

Figure 10

In Figure 11, the optimizer is used to assess and compare the potential performance gain achievable by a variety of proposed technology options. In this figure, the “base” case is the “baseline” 65-nm-node technology to which the other cases should be compared. Each point plotted is the peak performance that is possible with the given heat sink and the specified temperature rise, corresponding to the highest points on curves similar to those in Figure 6(a). Because the power level at which the peak occurs varies depending on the technology option, the data points are somewhat scattered along the x-axis. Among the options compared, the following appear to be effective for improving performance: reducing the wiring permittivity by 0.64x, using 3D integration with two layers of active circuitry, and turning off the supply to inactive logic. Reducing variability by 0.7x also helps performance somewhat, while simply making the wiring smaller does not appear very beneficial, as has already been discussed. Overall, technology changes that truly lower the switching energy appear useful, while changes that only make devices faster or denser at the same switching energy are not valuable when the circuits are power-limited. Because power is the controlling factor, improved heat removal is also quite effective. Note that maximum performance should be achieved by implementing all of the favorable changes simultaneously.

Figure 11

As noted above, improved heat-sink technology offers a direct path to larger performance gains than those provided by improved device technology, as shown in Figure 12. One may also gain a modest performance increase by decreasing the heat-sink temperature, but this performance gain generally disappears if the refrigerator power must be taken into account. Thermal solutions are difficult because such high-power processors are very inefficient, and performance is only increasing as roughly the log of the power. Note that it may not actually be possible to reliably deliver such high power levels to the chip, but experiments have shown that microchannel liquid cooling can remove the associated heat [24, 25].

Figure 12

This efficiency challenge is captured in Figure 13, which shows average energy dissipated per logic transition (total logic power divided by LTR) versus overall performance, for optimizations that cross technology generations by also including the wire pitch and the halo behavior among the optimized variables, yielding a total of nine variables being optimized. These optimizations are considered for four-core processor chips. Clearly, the very high-power designs are quite energy-inefficient, on a logic transition basis, compared to what is possible at lower power. The knee in this curve is very interesting, because it turns out to be within a factor of ~3 from both the lowest-energy designs and the highest-performance designs. Architectural innovations may allow most applications below and above the knee of this curve to efficiently utilize the device design at the knee, making the knee a very important technology design point.

Figure 13

One way to address the energy inefficiency of the high-power design points involves the use of smaller, lower-power cores in parallel. This is examined in Figure 14, in which a fixed number of transistors is divided into different numbers of processor cores. The cases with the higher numbers of cores have higher performance because the smaller cores result in relatively less wiring capacitance due to the shorter wires. This basic performance increase must of course be adjusted for architecture and system effects associated with increased parallelism, but these issues are outside the scope of this work.

Figure 14

Our results show very clearly that power constraints have a great effect on technology scaling. It is no longer possible to scale CMOS technology from one generation to another without taking into account power dissipation. Many of the proposed technology enhancements do show promise, but careful optimizations are necessary at every power level to ensure that the most appropriate technology is being used. The optimizations show that there is still room for significant progress in high-performance CMOS out to at least the 32-nm generation, especially for high-power applications, but low-power applications will require less-scaled devices. In the future, the dominant CMOS market may include technologies such as those with characteristics near the knee of Figure 13; however, smaller markets will undoubtedly continue to exist for both high-performance logic and very low-power technology.

The authors wish to thank M. Wisniewski, M. Scheuermann, P. Restle, S. Kosonocky, E. Colgan, and J. Magerlein for useful discussions and information.

¹The International Technology Roadmap for Semiconductors (ITRS) is an assessment of semiconductor technology requirements and is a cooperative effort of manufacturers, suppliers, government organizations, and universities.

Received October 3, 2005; accepted for publication December 22, 2005; Published online August 6, 2006.