Kerry Bernstein IBM Research Division, Thomas J. Watson Research Center, P.O. Box 218, Yorktown Heights, New York 10598 (kbernsteus.ibm.com). Mr. Bernstein is a Senior Technical Staff Member at the IBM Thomas J. Watson Research Center. He is currently responsible for future product technology definition, performance, and application. He received his B.S. degree in electrical engineering from Washington University in St. Louis, joining IBM in 1978. He holds 50 U.S. patents and is a coauthor of three college textbooks and multiple papers on high-speed and low-power CMOS. Mr. Bernstein is currently interested in the area of high-performance, low-power advanced circuit technologies. He is a Senior Member of the IEEE, and is a staff instructor at RUNN/Marine Biological Laboratories, Woods Hole, Massachusetts.

David J. Frank IBM Research Division, Thomas J. Watson Research Center, P.O. Box 218, Yorktown Heights, New York 10598 (djfus.ibm.com). Dr. Frank received a B.S. degree from the California Institute of Technology in 1977 and a Ph.D. degree in physics from Harvard University in 1983. Since graduation, he has worked at the IBM Thomas J. Watson Research Center, where he is a Research Staff Member. His studies have included non-equilibrium superconductivity, III–V devices, and exploring the limits of scaling of silicon technology. His recent work includes the modeling of innovative Si devices, analysis of CMOS scaling issues such as power consumption, discrete dopant effects and short-channel effects associated with high-k gate insulators, exploring various nanotechnologies, investigating the usefulness of energy-recovering CMOS logic and reversible computing concepts, and low-power circuit design. Dr. Frank is an IEEE Fellow; he has served as chairman of the Si Nanoelectronics Workshop and is an associate editor of the IEEE Transactions on Nanotechnology. He has authored or co-authored more than 90 technical publications and holds nine U.S. patents.

Anne E. Gattiker IBM Research Division, Austin Research Laboratory, 11501 Burnet Road, Austin, Texas 78758 (gattikerus.ibm.com). Dr. Gattiker holds a Ph.D. degree from Carnegie Mellon University, where she was a National Science Foundation Fellow. Since joining IBM in 1998, she has worked in the IBM Worldwide Test Engineering group in Burlington, Vermont, and at the IBM Austin Research Laboratory in Austin, Texas, where she is a Research Staff Member. Her research interests include design-for-manufacturability and variability characterization, as well as defect-based test, reliability screens, and defect diagnosis. Dr. Gattiker has published more than twenty technical papers, has participated on numerous conference panels, and has been a co-winner of best paper awards at the IEEE International Test Conference and the IEEE International Conference on Microelectronic Test Structures. She is the ITC Technical Program Chair in 2006 and is on the program committees of ITC and the ASM International Symposium on Testing and Failure Analysis.

Wilfried Haensch IBM Research Division, Thomas J. Watson Research Center, P.O. Box 218, Yorktown Heights, New York 10598 (whaenschus.ibm.com). In 1981, Dr. Haensch received his Ph.D. degree from the Technical University of Berlin, Germany, in the field of theoretical solid-state physics. In 1984 he joined Siemens Corporate Research in Munich to investigate high-field transport in MOSFET devices, and in 1988 he joined the DRAM development team at the Siemens Research Laboratory to investigate new cell concepts. In 1990, he joined the DRAM alliance between IBM and Siemens to develop quarter-micron 64M DRAM. In this capacity, Dr. Haensch was involved with device characterization of shallow-trench bounded devices and cell-design concerns. In 1996, he moved to a manufacturing facility to build various generations of DRAM. His primary mission was to transfer technologies from development into manufacturing and to guarantee a successful yield ramp of the product. In 2001, Dr. Haensch joined the IBM Thomas J. Watson Research Center to lead a group concerned with novel devices and applications. He is currently responsible for post-45-nm-node device design and its implications for circuit functionality.

Brian L. Ji IBM Research Division, Thomas J. Watson Research Center, P.O. Box 218, Yorktown Heights, New York 10598 (bljius.ibm.com). Dr. Ji received a B.S. degree from the University of Science and Technology of China, Hefei, in 1984, and a Ph.D. degree in physics from Harvard University in 1991. From 1991 to 1994, he was a research scientist at SUNY at Stony Brook, where he studied nanofabrication, single-electron memory/logic devices, and superconducting devices. He was a visiting scientist in physical sciences at the IBM Thomas J. Watson Research Center in 1995. The following year he joined the IBM Microelectronics Division in Hopewell Junction, New York, where he worked on several projects in VLSI circuit design, test, and product definition, including 256-Mb, 512-Mb, and 1-Gb DRAMs, and the logic-based embedded memory. From 2001 to 2005 Dr. Ji was involved in analog design for high-speed serial link products. Since 2005, he has been a researcher at the IBM Thomas J. Watson Research Center, studying a number of issues in silicon devices, circuits, and systems, including technology variability, SOI SRAM, and exploratory low-power circuits.

Sani R. Nassif IBM Research Division, Austin Research Laboratory, 11501 Burnet Road, Austin, Texas 78758 (nassifus.ibm.com). Dr. Nassif received a Ph.D. degree from Carnegie Mellon University in the 1980s. He worked for ten years at Bell Laboratories on various aspects of design and technology coupling, including device modeling, parameter extraction, worst-case analysis, design optimization, and circuit simulation. In 1996 Dr. Nassif joined the IBM Austin Research Laboratory, where he currently manages the Tools and Technology Department, which is focused on design/technology coupling and includes activities in model-to-hardware matching, simulation and modeling, physical design, statistical modeling, statistical technology characterization, and similar areas.

Edward J. Nowak IBM Systems and Technology Group, 1000 River Street, Essex Junction, Vermont 05452 (ejnowakus.ibm.com). Dr. Nowak received his B.S. degree in physics in 1973 from M.I.T., and M.S. and Ph.D. degrees, also in physics, from the University of Maryland in 1975 and 1978, respectively. In 1981, following postdoctoral research at New York University, he joined IBM in Essex Junction, Vermont, to work on DRAM development. Since 1985, Dr. Nowak has worked in high-performance CMOS device design. His current interests include energy-driven device design and FinFET device architectures.

Dale J. Pearson IBM Research Division, Thomas J. Watson Research Center, P.O. Box 218, Yorktown Heights, New York 10598 (dale_pearsonus.ibm.com). Mr. Pearson received a B.S. degree in chemistry from Texas Lutheran University in 1979 and an M.S. degree from the University of Wisconsin at Madison in 1981. After working in the IBM Microelectronics Division and the General Electric Corporation, in 1984 he joined the IBM Research Division, where he has worked and directed efforts on Cu VLSI wiring, process technology for low-T_c superconducting circuits, communications VLSI circuit design, and product development and circuit techniques to manage and mitigate VLSI process variability. Mr. Pearson is currently the Associate Director for Systems Research at the IBM Thomas J. Watson Research Center.

Norman J. Rohrer IBM Systems and Technology Group, 1000 River Street, Essex Junction, Vermont 05452 (rohrernus.ibm.com). Dr. Rohrer is a Distinguished Engineer in the IBM Systems and Technology Group, Essex Junction, Vermont. In 1987 he received a bachelor's degree in physics and mathematics from Manchester College, North Manchester, Indiana. He received a master's degree and a Ph.D. degree in electrical engineering from Ohio State University, Columbus, in 1990 and 1992, respectively. Dr. Rohrer has been a lead designer on PowerPC 750 and 970 products for the Apple G3 and G5 chips and the Nintendo GameCube**. His interests lie in the area of high-speed circuit optimization for future technologies. He holds 22 patents and is a coauthor on two books titled High Speed CMOS Circuit Design Styles and SOI Circuit Design Concepts. Dr. Rohrer has been a Senior Member of the IEEE since 2003.

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