Continuous MOSFET performance increase with device scaling: The role of strain and channel material innovations

Conventional MOSFETs have proven to be remarkably scalable to gate lengths of about 60 nm, which are compatible with the 130-nm high-performance CMOS technology node. Intrinsic device performance up to this node has increased by about 17% per year, following an inverse gate-length (1/L_g) dependence commensurate with channel length decrease. This performance increase has relied in part on the steady increase of channel carrier velocity due to gate-length scaling combined with innovations, such as super-steep retrograde channel doping, and highly doped halos around very highly doped source and drain junctions. However, the intrinsic carrier transport properties in the channel material have remained constant, i.e. those of the relaxed silicon lattice; from the 90-nm node onward, additional innovations have been introduced to increase channel carrier mobilities, and hence allow continuation of velocity increase, by the imposition of process-induced strain in the silicon channel of otherwise conventional MOSFETs. The introduction of strain into the Si channel at the 90-nm node (see for example [1]) has been critical to increasing carrier mobility and velocity in the channel and maintaining historical CMOS performance trends. In Section 2 of this paper, a model is developed that quantitatively illustrates the relationship among carrier velocity, MOSFET drain current, and switching time. Carrier velocity is extracted from published data, and its historical progression is plotted as a function of gate length. From the analysis, it is clear that additional improvements in channel velocity and therefore in mobility will be required in order for commensurate scaling (delay inversely proportional to gate length) to continue. Section 3 reviews the status of research efforts to improve electron and hole mobility using heterostructures of strained Si and strained SiGe, on both bulk and on-insulator substrates. Section 4 contains a discussion of some remaining challenges associated with these heterostructure MOSFETs, and the paper concludes in Section 5.

The drain saturation current in a MOSFET normalized to the channel width, I_D/W, can be approximated as follows:

where Q’_s is the channel charge areal density at the virtual source, C’_oxinv is the gate-to-channel capacitance per unit area at inversion, and v is the effective carrier velocity at the virtual source, which is thus defined as the point in the channel at which the charge density is given by C’_oxinv(V_G − V_t). V_G is the applied gate–source voltage, and V_t is the effective threshold voltage in saturation, i.e., obtained from linear extrapolation of the I_D–V_G curve to I_D = 0; V_t is given by

where V_t0 is the effective threshold voltage at drain-to-source voltage V_D, equal to zero, and δ is the drain-induced barrier-lowering (DIBL) coefficient. On the other hand, the intrinsic MOSFET switching delay, , is given by

(3)

where ΔQ_G is the charge difference at the gate electrode between the two logic states, including both channel charge and intrinsic gate electrode fringing capacitance charge, and is given by

and I_eff is the effective MOSFET switching current [2] given by

ERROR: The last term of Equation (5) should be multiplied by v. See published errata.
The corrected equation follows:

Using Equations (4) and (5) in (3) results in

(6)

where V_dd is the supply voltage and C*_f is the total effective gate fringing capacitance, including all internal and external fringing capacitances, with the Miller effect on the drain side taken into account. It is interesting to note that C*_f is nearly independent of technology generation for properly scaled devices [3], with a value of about 0.5 fF/μm.

Because of the existence of finite resistance between the source contact (and the drain contact) and the channel, R_s, the actual carrier velocity at the virtual source, v_xo, can be approximated by

(7)

The virtual source point is located near the top of the potential barrier between source and channel, and v_xo is related to the so-called source injection velocity, v_θ, or ballistic-limit velocity, as discussed by Lundstrom [4]. Figure 1 illustrates these concepts. Exact evaluation of v_xo has been described in [5]. The ballistic velocity v_θ for electrons vs. effective electric field in the channel is plotted in Figure 2, for both relaxed and strained Si using a self-consistent Schroedinger–Poisson solver, SCHRED [6]. For the strained Si it was assumed that only the Δ₂ valleys are populated, with no other changes relative to relaxed Si. The assumption that all electrons occupy the Δ₂ valleys corresponds roughly to an energy splitting between the Δ₂ and Δ₄ valleys greater than 140 meV, or a biaxial tensile strain level higher than approximately 1%.

Figure 1 Figure 2

While Equation (1) has been used primarily to model transistors in the ballistic limit, it actually fits state-of-the-art transistor data over the period of the last two decades. Indeed, close examination of selected (bulk-Si) publications [7–15] allows v_xo for both electrons and holes to be tracked over the same period of time, for gate length L_g ranging from 480 nm to 35 nm. In those selected publications, C_oxinv is given or can be estimated accurately, δ can be extracted from the data, and R_s (or at least its upper bound) can be reasonably estimated from the output I–V characteristics near V_D = 0. In the data analyzed, values of the denominator in Equation (7) were typically higher than 0.80, indicating no more than ~20% correction to the raw extracted velocity, v. The values of v_xo extracted from the literature data are shown in Figure 3, as well as the required electron and hole velocities at L_g = 10 nm in order to continue the historical reduction of delay in direct proportion to L_g, as discussed below. As can be seen for both electrons and holes, the carrier velocity v_xo has been steadily increasing with decreasing L_g. For all gate lengths down to 60 nm, the channel is unstrained (100) silicon, and therefore the carrier mobility vs. effective field relationship has been essentially unchanged. The main reason for the general trend of velocity increase with scaling can be understood from the scattering theory [4] as being due to reduction of the characteristic length of the potential barrier near the source, as L_g is scaled, and therefore reduction of backscattering. This reduction in the characteristic length of backscattering has been the result of proper scaling of the electrostatic design of MOSFETs, and has been achieved via innovations in source/drain and channel doping engineering. The key point here is that v_xo should increase (provided v_xo is smaller than v_θ) when there is a reduction in backscattering, either by reduction of the length over which backscattering can occur, which is the case here, or by reduction of the scattering rate. However, closer examination of the data shows that from L_g ~ 130 nm to 60 nm there has actually been a saturation of velocity increase that is most likely due to the increase of coulombic scattering near the source associated with increase in doping that counterbalances the decrease in the backscattering effective length.

Figure 3

Below 60 nm, the increase in velocity observed in Figure 3 is due to the introduction of well-known strain-induced mobility increases in the channel via innovative process steps [14, 15], which has brought about a decrease in the backscattering rate. With channel carrier mobility being a proxy for the inverse of the backscattering rate, it has been found experimentally via the application of strain that in short-channel devices there exists a ~0.5 ratio of proportionality between channel electron or hole velocity and mobility [1, 16]. An additional effect contributing to this proportionality ratio may also be the fact that the ballistic injection velocity increases because of the reduction in the carrier effective mass by applying strain. At first sight, it would appear that both n- and p-MOSFETs are approaching the ballistic limit after these innovations, but as Figure 2 shows (for electrons), this is not necessarily the case, because the injection velocity is also increasing. The electron injection velocity would be even higher with uniaxial strain along the <110> channel direction as a result of decreased effective mass [17].

MOSFET intrinsic delay calculated from extracted historical device data and Equation (5) is shown in Figure 4 for n- and p-MOSFETs. Also shown are the projected intrinsic delays at L_g = 10 nm, using the corresponding extrapolated velocities of Figure 3 and making some more or less optimistically reasonable assumptions about device electrostatics (i.e., δ = 0.1 V/V, subthreshold swing about 90 mV/decade resulting in I_off ~ 300 nA, at V_dd = 0.8 V. The last two values are from the 2004 International Technology Roadmap for Semiconductors (ITRS '04) [18] for L_g = 10-nm devices (22-nm high-performance node).

Figure 4

It is notable that historically the increase in velocity and therefore the steeper-than-L_g decrease of the L_g/v term has counterbalanced a parallel increase in the prefactor to that term in Equation (6), resulting in near-perfect proportionality between and L_g. Continuous improvement in intrinsic delay with scaling will require increasingly higher velocities, and at least for electrons in silicon, even with uniaxial strain, the velocity would have to approach the theoretical ballistic velocity as we approach 10-nm gate lengths. This would suggest that, at least for n-FETs, this is not likely to happen in silicon channels.

It is clear from this discussion that the increase in channel carrier velocity results from backscattering reduction, and while some of it may result from further scaling of the characteristic length for backscattering, the channel mobility increase is, from this point in time onward, the main lever for continuing the historical decrease of transistor delay in proportion to L_g. Prospects for continued channel mobility increase are discussed in the following sections.

Although process-induced stress has been used to achieve significant mobility enhancements in short-channel devices (e.g., ~2x for holes in 65-nm technology [15]), the Si/SiGe materials system has the potential to achieve very large improvements in mobility (e.g., ~10x hole-mobility enhancements for strained Ge channels), as discussed below. The following two sections review the status of research on Si/SiGe heterostructure MOSFETs in bulk and on-insulator technologies.

Figure 5 schematically illustrates various heterostructure substrates that have been used to investigate biaxial strain and high-mobility channel materials, including epitaxial structures on bulk substrates and on-insulator implementations. The on-insulator (“OI”) substrates are generally derived from bulk structures by a combination of epitaxial growth, wafer bonding, and delamination or etch-back methods, which preserve the strain state of the layers. For example, strained silicon directly on insulator (SSDOI), illustrated in Figure 5(e), is derived from biaxial strained Si/relaxed Si_1−xGe_x by transfer of the epitaxial layers and removal of the relaxed Si_1−xGe_x virtual substrate, leaving a strained Si layer directly in contact with silicon dioxide [19–21]. The on-insulator technologies provide a pathway to implementing mobility enhancement in partially or fully depleted devices, in ultrathin-body MOSFETs, or nonplanar (e.g., double-gate) MOSFETs, and are discussed in the next subsection. This section focuses on the investigation of mobility in bulk MOSFETs.

Figure 5

Figure 6 compares effective mobility in bulk MOSFETs for (a) electrons in strained Si/relaxed SiGe and (b) holes in Si-channel and strained Si/Si_1−yGe_y dual-channel heterostructures. Dual-channel heterostructures [Figure 5(b)] use a combination of strained Si and strained Si_1−yGe_y to enable simultaneously high electron and hole mobilities [23–25]. In addition, because of the high Ge content and compressive strain, these structures offer significantly higher hole mobility than either biaxial-tensile strained Si [Figure 6(b), ○] or process-induced strained Si [Figure 6(b), □]. As illustrated in Figure 6(b), the hole mobility increases with increasing Ge fraction in the strained Si_1−yGe_y channel. A hole-mobility enhancement factor of approximately 10x, relative to unstrained Si, is obtained for a p-MOSFET with a thin strained Si layer (~5 nm) on top of a strained Ge channel (~12 nm) on a relaxed Si_0.5Ge_0.5 virtual substrate [25]. The electron mobility in the strained Si channel is enhanced by approximately a factor of 2 for the same structure. The high hole mobility results from a combination of the small Ge in-plane hole effective mass, the biaxial-compression-induced strain splitting of the valence bands, and the use of a thin Si cap layer, which enables a low interface state density to be obtained at the semiconductor/insulator interface. In Ge surface-channel MOSFETs, where the gate dielectric is formed directly on Ge without an intermediate Si layer, reported hole-mobility enhancements are in the range of 1.4 to 2x [27–29], and n-MOSFET performance is disappointing [30]. The use of Si-compatible gate insulator technology makes the strained Si/strained Ge dual-channel heterostructure very attractive.

Figure 6

Detailed understanding of dual-channel MOSFET operation requires information on the energy bands for the heterostructure. The energy band lineup for bulk 70/40 dual-channel p-MOSFETs is illustrated schematically in Figure 7 (the notation y/x represents the Ge percentages in the strained Si_1−yGe_y layer and in the relaxed Si_1−xGe_x substrate, respectively). The large valence band offset (~0.5 eV) confines holes to the high-mobility strained Si_1−yGe_y channel. Due to the band lineup, an electron inversion layer forms in the strained Si layer in the n-MOSFET, while in the p-MOSFET, hole inversion occurs first in the high-mobility strained SiGe layer, and, at higher gate overdrive, in the strained Si cap layer, assuming a sufficiently thick Si cap layer. If the Si cap is thin (~2 nm), holes can be forced into the Si_1−yGe_y, resulting in high mobility even at high inversion charge densities. The impact of the Si cap thickness on mobility is illustrated in Figure 8, which shows the measured hole-mobility enhancement factor, relative to Si control devices, for 70/40 dual-channel p-MOSFETs [32]. For the thinnest Si cap, mobility enhancements of 3x are obtained at all inversion charge densities measured (up to 1.3 × 10¹³ cm⁻²). The Si cap thickness was extracted on each device by fitting simulations to measured capacitance voltage (C–V) characteristics, as discussed in the next subsection.

Figure 7 Figure 8

A challenge for these structures is illustrated in Figure 9. Measured off-state drain current is higher for dual-channel p-MOSFETs than for similarly processed Si control devices. The leakage occurs in the drain/gate overlap region, and the temperature dependence suggests a combination of band-to-band and trap-assisted tunneling [32]. The leakage increases with increasing Ge fraction, x in the substrate and y, in the Si_1−yGe_y channel, consistent with a reduction in the bandgaps of the strained Si and SiGe channel layers [32]. Drain leakage has also been observed in narrow-bandgap pseudomorphic Si/Ge/Si p-MOSFETs grown on unstrained Si [33]. These authors report reduced leakage for ultrathin Ge channels (~3 nm), though this also reduces the mobility enhancement. Detailed understanding requires further investigation, especially of the material quality in the ion-implanted gate/drain overlap region, which is subject to damage-enhanced interdiffusion of the Si and SiGe [34]. Optimization of the process should reduce trap densities in this region and the off-state leakage. Although the narrow bandgap of high-Ge-content SiGe may be associated with increased leakage, the reduction in the “effective bandgap” of the heterostructure (the energy difference between E_c in strained Si and E_v in strained SiGe, illustrated in Figure 7), relative to unstrained Si, has a positive implication: A single metal gate material, with a workfunction near the “mid-gap” of the heterostructure, may be utilized for both n- and p-MOSFETs, yielding appropriate threshold voltages [35, 36].

Figure 9

A remaining challenge of these structures is the fact that the p-MOSFET, even with a 1-nm-thick Si cap layer, is not strictly a surface-channel device, and thus the electrostatics are somewhat compromised. For heavily doped substrates and thin gate oxides, this results in a larger subthreshold swing than observed for Si control devices [37]. The ideal subthreshold swing is recovered when the heterostructures are fabricated into fully depleted on-insulator MOSFETs, as discussed below. Simulations of the scalability of these structures are discussed in the following subsection.

Strained Si/strained SiGe heterostructure on insulator (HOI) combines the transport benefits of the dual-channel structure with the electrostatics of fully depleted SOI (FD–SOI), and the potential to scale the body thickness into the ultrathin regime. To fabricate HOI, strained Si/strained SiGe/strained Si is grown on relaxed Si_1−xGe_x, and the top three layers are transferred to the insulator, with the original strain state preserved in the transfer process, as illustrated in Figure 10 [38]. A similar process may be used to fabricate strained Si directly on the insulator, with “x% SSDOI” referring to the Ge fraction of the relaxed Si_1−xGe_x in the donor substrate. In HOI, the strained Si on either side of the SiGe layer reduces the interface state density at the semiconductor/dielectric interface, compared with devices in which the SiGe is in direct contact with the oxide (see for example [39] for a discussion of SiGe/oxide interface quality). In HOI, the lower strained Si layer also has the potential to serve as a second (bottom) channel for electrons, in double-gate structures. The top strained Si layer serves as the electron channel in the n-MOSFET, and it can be selectively thinned to a thickness of 1 to 2 nm on the p-MOSFET to enable near-surface-channel operation with Si-compatible gate dielectric technology.

Figure 10

HOI has been fabricated with up to 55% Ge in the Si_1−yGe_y channel, and donor-wafer relaxed SiGe layers with Ge content of 25% (“55/25 HOI”) [40]. A reduced thermal budget process is used for both substrate fabrication (maximum bond anneal 600°C, 2.5 hr) and MOSFET processing (600°C, 5-hr gate oxidation, and 800°C 10-s source/drain activation) [40]. As in dual-channel MOSFETs, control of the strained Si cap thickness is critical to the operation of HOI MOSFETs. The Si cap thickness on the p-MOSFET can be extracted from a combination of C–V measurements and simulations, as illustrated in Figure 11. Calculations using the Dessis simulator [42] are employed, and quantum effects are taken into account using the density gradient correction model, with density of state values modified for strained Si and models verified on bulk dual-channel devices [31]. Figure 12(a) shows simulated hole-density distributions as a function of distance from the strained Si/SiGe interface, in 46/25 HOI. As illustrated in the figure, thin Si cap layers (~2 nm) result in a hole distribution that is primarily in the high-mobility, compressively strained SiGe, even at high inversion charge densities of 10¹³ cm⁻². Such thin-cap HOI devices enable constant hole-mobility enhancement as a function of inversion charge density, illustrated in Figure 12(b).

Figure 11 Figure 12

Figure 13 compares electron and hole mobilities in SSDOI and HOI [40]. Mobility in co-fabricated SOI control devices is close to the published universal mobility curves (dashed lines) [26]. For electrons [Figure 13(a)], mobilities in HOI and in corresponding SSDOI are similar, though slightly degraded in HOI, perhaps associated with the finite Si cap thickness (5 nm) and the impact of Ge from the underlying SiGe layer, which is  absent in  SSDOI. For  holes [Figure 13(b)], very high strain levels (e.g., 40% SSDOI) are required to achieve hole-mobility enhancement in tensile-strained Si at high inversion charge densities, N_inv. This can be explained by quantization effects that reduce the strain-induced splitting of the valence bands in strong inversion, for the case of biaxial tensile strain in Si [44, 45]. In compressively strained Si (biaxial or uniaxial), quantization effects are not expected to counteract the strain-induced valence band splitting; thus, hole-mobility enhancement should be relatively constant with increasing inversion charge density (as observed in p-MOSFETs with Si channels under compressive stress [46]). When compressive stress is applied to SiGe, constant hole-mobility enhancement may also be expected with inversion charge density, because of the similarity of the Si and SiGe valence band structure. Indeed, as illustrated in Figure 13(b), the hole-mobility enhancement in compressively strained 46/25 HOI is maintained at large inversion charge density, and is significantly larger than that observed in 40% SSDOI.

Figure 13

Figure 14 compares long-channel subthreshold characteristics for 25% SSDOI and 55/25 HOI n- and p-MOSFETs. Low subthreshold swing is achieved in fully depleted HOI MOSFETs in spite of the buried SiGe channel, an advantage compared with bulk dual-channel heterostructure devices [37]. The issue of elevated off-state leakage relative to SSDOI or SOI control devices, discussed above for bulk heterostructures, remains in HOI. Thinning the SiGe layer from 10 nm to 4 nm reduces the off-state leakage by roughly a factor of 3, but the mobility is also reduced, as illustrated in Figure 15 [40]. Further study of the leakage mechanisms is required in order to understand the tradeoffs between enhanced mobility and drain leakage.

Figure 14 Figure 15

The behavior of these new heterostructure materials in short-channel devices requires investigation. The electrostatics for the p-MOSFET have been simulated to evaluate the impact of the heterostructure on scalability. Figure 16 compares simulated subthreshold swing (SS) for 46/25 HOI and SOI p-MOSFETs of equal body thickness, assuming 1-nm-thick Si cladding layers on either side of the SiGe layer (i.e., T_body = 1 nm Si + T_SiGe + 1 nm Si). The physical device parameters were taken from the International Roadmap for Semiconductors (ITRS) [18], assuming a fixed equivalent oxide thickness of 1 nm. For gate lengths down to 20 nm, subthreshold swing in HOI is only slightly increased (~15%), compared with that for SOI, for total film thicknesses T_body less than or equal to 6 nm. This SS increase originates from the decreased semiconductor capacitance associated with the displacement of the hole charge centroid from the oxide/semiconductor interface. When the body thickness is comparable to the inversion layer thickness (e.g., 4 nm), the subthreshold swing of the HOI device approaches that of the SOI device. At this thickness, however, the hole-mobility enhancement is expected to decrease as the SiGe channel layer is thinned. Investigation of transport in short-channel devices incorporating these new materials is a topic for future research.

Figure 16

Although the mobilities achieved in long-channel strained Si/strained SiGe heterostructures on bulk and insulator are promising, there are significant practical challenges associated with implementing these materials in a manufacturable CMOS technology, including material quality of the as-grown epitaxial layers, process integration issues such as interdiffusion between thin Si and SiGe layers, and the potential for formation of defects in strained layers during processing. Progress in these challenging areas has been achieved. Significant improvements have been demonstrated in reducing the defect densities in relaxed SiGe layers on Si substrates [47]. Interdiffusion at Si/SiGe interfaces is being studied and limits the thermal budget as the Ge content is increased because of the strong dependence of the interdiffusivity on Ge fraction and strain [48]. Laser annealing may be a solution to this issue. Enhanced diffusion of dopants along misfit dislocations at the strained Si/SiGe interface has been associated with increased off-state leakage in short-channel MOSFETs, and the strained Si thickness and Ge fraction in the SiGe layer must be limited, for a given thermal budget, to prevent this phenomenon [49, 50]. It should be noted that many of these challenges are associated with the presence of SiGe during CMOS processing, and that SSDOI thus has the potential for simpler process integration than HOI structures (but with less mobility leverage for p-MOSFETs).

Additional research on gate dielectric materials to be used with these structures is required. High-k dielectrics have been employed on strained Si surface-channel n-MOSFETs, and can be used to recover the mobility loss associated with high-k insulators such as HfO₂ on Si [22, 51]. A potential benefit of devices incorporating strained Si on SiGe is the possibility of reduced gate leakage currents, associated with the increased barrier height at the semiconductor/gate dielectric interface due to the strain-induced lowering of the conduction-band energy [52]. An additional challenge for Ge-containing devices is the need for a high-quality high-k gate dielectric that can be formed directly on SiGe or Ge. High-k gate dielectrics (e.g., TiN gate electrode with HfO₂ dielectric) have been demonstrated directly on Si_0.7Ge_0.3, with 1.5x hole-mobility enhancement, but gate leakage currents were larger than for Si control devices [53]. Until a high-quality gate insulator for SiGe or Ge is developed, a thin (~1-nm) Si cap layer, which enables the use of Si-compatible gate technology, is a reasonable compromise for the p-MOSFET. High-k gate stacks with metal gate electrodes (TiN/HFO₂) have been demonstrated on strained SiGe channels, with thin sacrificial Si layers (~1 nm) used to improve the interface quality [36], and on MOSFETs incorporating strained Si (2.5 nm thick)/strained Ge (7 nm thick) on relaxed SiGe (50% Ge) with 9x hole-mobility improvement over Si control devices [54]. Thus, the use of high-k gate stacks with strained Si/strained Ge is expected to enjoy the same large mobility enhancements demonstrated in earlier work using SiO₂ gate dielectrics [25].

An area of interest for future work is the combined use of global and local stress techniques, for example by the application of process-induced stress (Si₃N₄ etch-stop liners over the gate) to devices containing initially biaxially strained Si or Ge channels. Such methods may offer larger enhancements than can be obtained from either process-induced or global stress techniques alone. This concept is illustrated in [55], where the impact of mechanical stress on SOI and SSDOI devices is studied. In that work, biaxial tensile strain in the Si is used to split the conduction-band degeneracy and repopulate all electrons into the Δ₂ conduction band. Superimposed on this stress is a uniaxial component along the [110] direction, induced by mechanical bending, which deforms the Δ₂ band, i.e., induces a change in the effective mass. Such effective mass changes are important in short-channel devices because of the impact of effective mass on the Coulomb-scattering-limited channel mobility.

The application of these enhanced-mobility materials to nonplanar devices, such as FinFETs or tri-gate structures, requires investigation. Patterning-induced changes in strain and mobility also require study. Patterning of initially biaxially strained SiGe films on insulator has been used to produce uniaxially strained SiGe p-MOSFETs with improved short-channel mobilities [56]. The passivation of SiGe heterostructures will remain an issue, since nonplanar devices inherently have a large surface-to-volume ratio. Finally, since InGaAs and related compounds have very high electron mobilities (of the order of 10,000 cm²/V-s), these materials are attractive for investigation as high-performance n-FETs on Si substrates. When coupled with the high hole mobility in strained Ge, a III–V/Ge channel pair may be of interest for future n- and p-FET logic devices.

A simple model that links MOSFET performance to effective carrier velocity in the channel has been developed and used to extract electron and hole velocities in Si MOSFETs from published electrical data. The impact of improved mobility associated with process-induced strain is evident from the extracted carrier velocities. From the analysis of carrier velocity and its effect on intrinsic device switching delay, it is clear that additional improvements in velocity (and hence channel mobility) beyond those that have been achieved with process-induced stress will be required in order for commensurate scaling (delay inversely proportional to channel length) to continue. Research on long-channel MOSFETs has demonstrated that significant mobility enhancements (e.g., 2x for electrons and 10x for holes) relative to Si MOSFETs can be achieved in the strained Si/strained SiGe materials system. On-insulator analogs of these bulk heterostructure devices (e.g., SSDOI and HOI) have been demonstrated, with encouraging mobility and subthreshold characteristics. Associated with these heterostructures are several fundamental tradeoffs, such as the mobility enhancement and the leakage current, both of which increase with Ge content. The heterostructure must be optimized with such tradeoffs in mind. There are also enormous practical challenges in implementing these heterostructures in a manufacturing technology. The higher mobility offered by SiGe, Ge, and III–V semiconductors on silicon, and the improvements in lattice-mismatched epitaxial growth, continue to make these heterostructures a promising and active area of device research.

This work was supported by research contracts from the Microelectronics Advanced Research Corporation (MARCO) and the Semiconductor Research Corporation (SRC).

Received October 20, 2005; accepted for publication February 28, 2006; Published online June 27, 2006.