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IBM Journal of Research and Development
Exploratory Systems Research   Volume 50, Number 2/3, 2006
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HeapMon: A helper-thread approach to programmable, automatic, and low-overhead memory bug detection - References

 by R. Shetty,
M. Kharbutli,
Y. Solihin,
and M. Prvulovic
References

  1. IBM Corporation, IBM Rational PurifyPlus for UNIX; see http://www-306.ibm.com/software/awdtools/purifyplus/.
  2. P. Zhou, F. Qin, W. Liu, Y. Zhou, and J. Torellas, “iWatcher: Efficient Architectural Support for Software Debugging,” Proceedings of the 31st Annual International Symposium on Computer Architecture, 2004; see http://opera.cs.uiuc.edu/paper/ZhouISCA04.pdf.
  3. T. M. Austin, S. E. Breach, and G. S. Sohi, “Efficient Detection of All Pointer and Array Access Errors,” Proceedings of the ACM SIGPLAN Conference on Programming Language Design and Implementation, 1994, pp. 290–301.
  4. C. Cowan, C. Pu, D. Maier, H. Hinton, J. Walpole, P. Bakke, S. Beattie, A. Grier, P. Wagle, and Q. Zhang, “StackGuard: Automatic Adaptive Detection and Prevention of Buffer-Overflow Attacks,” Proceedings of the 7th USENIX Security Symposium, 1998, pp. 63–78.
  5. S. Hangal and M. S. Lam, “Tracking Down Software Bugs Using Automatic Anomaly Detection,” Proceedings of the International Conference on Software Engineering, 2002, pp. 291–301.
  6. Intel Corporation, Intel Thread Checker; see http://www.intel.com/cd/software/products/asmo-na/eng/threading/219783.htm.
  7. A. Loginov, S. H. Yong, S. Horwitz, and T. W. Reps, “Debugging via Run-Time Type Checking,” Lecture Notes in Computer Science 2029, 217–232 (2001).
  8. G. C. Necula, S. McPeak, and W. Weimer, “CCured: Type-Safe Retrofitting of Legacy Code,” Proceedings of the 29th ACM SIGPLAN-SIGACT Symposium on Principles of Programming Languages, 2002, pp. 128–139.
  9. H. Patil and C. Fischer, “Low-Cost, Concurrent Checking of Pointer and Array Accesses in C Programs,” Software Pract. & Exper. 27, No. 1, 87–110 (1997).
  10. H. Patil and C. N. Fischer, “Efficient Run-time Monitoring Using Shadow Processing,” Proceedings of the 2nd International Workshop on Automated and Algorithmic Debugging, 1995, pp. 119–132.
  11. IBM Corporation, Rational software; see http://www-306.ibm.com/software/rational/.
  12. S. Savage, M. Burrows, G. Nelson, P. Sobalvarro, and T. Anderson, “Eraser: A Dynamic Data Race Detector for Multithreaded Programs,” ACM Trans. Computer Syst. 15, No. 4, 391–411 (1997).
  13. Valgrind Developers, Valgrind; see http://valgrind.kde.org/.
  14. J. Boletta, SecurityFocus Newsletter No. 172, 2002; see http://www.pantek.com/library/linux/lists/securityfocus.com/sf-news/msg00002.html.
  15. Symantec Corporation, “Microsoft IIS HTR Chunked Encoding Heap Overflow Allows Arbitrary Code”; see http://securityresponse.symantec.com/avcenter/security/Content/2033.html.
  16. United States Computer Emergency Readiness Team, “Buffer Overflow in Microsoft Internet Explorer,” Technical Cyber Security Alert TA04-315A; see http://www.us-cert.gov/cas/techalerts/TA04-315A.html.
  17. United States Computer Emergency Readiness Team, “ ‘Code Red’ Worm Exploiting Buffer Overflow in IIS Indexing Service DLL,” FedCIRC Advisory FA-2001-19; see http://www.us-cert.gov/federal/archive/advisories/FA-2001-19.html.
  18. M. Musuvathi, D. Y. W. Park, A. Chou, D. R. Engler, and D. L. Dill, “CMC: A Pragmatic Approach to Model Checking Real Code,” Proceedings of the 5th Symposium on Operating Systems Design and Implementation, 2002, pp. 75–88.
  19. U. Stern and D. L. Dill, “Automatic Verification of the SCI Cache Coherence Protocol,” Proceedings of the Conference on Correct Hardware Design and Verification Methods, 1995, pp. 21–34.
  20. J.-D. Choi, K. Lee, A. Loginov, R. O'Callahan, V. Sarkar, and M. Sridharan, “Efficient and Precise Datarace Detection for Multithreaded Object-Oriented Programs,” Proceedings of the ACM SIGPLAN Conference on Programming Language Design and Implementation, 2002, pp. 258–269.
  21. D. Engler and K. Ashcraft, “RacerX: Effective, Static Detection of Race Conditions and Deadlocks,” Proceedings of the 19th ACM Symposium on Operating Systems Principles, 2003, pp. 237–252.
  22. S. Hallem, B. Chelf, Y. Xie, and D. Engler, “A System and Language for Building System-Specific, Static Analyses,” Proceedings of the ACM SIGPLAN Conference on Programming Language Design and Implementation, 2002, pp. 69–82.
  23. P. Zhou, W. Liu, L. Fei, S. Lu, F. Qin, Y. Zhou, S. Midkiff, and J. Torellas, “AccMon: Automatically Detecting Memory-Related Bugs via Program Counter-Based Invariants,” Proceedings of the 37th International Symposium on Microarchitecture, 2004, pp. 269–280.
  24. F. Qin, S. Lu, and Y. Zhou, “SafeMem: Exploiting ECC-Memory for Detecting Memory Leaks and Memory Corruption During Production Runs,” Proceedings of the 11th International Symposium on High-Performance Computer Architecture, 2005; see http://www.hpcaconf.org/hpca11/papers/28_qin-safemem.pdf.
  25. M. L. Corliss, E. C. Lewis, and A. Roth, “Low-Overhead Interactive Debugging via Dynamic Instrumentation with DISE,” Proceedings of the 11th International Symposium on High-Performance Computer Architecture, 2005, pp. 303–314.
  26. J. Oplinger and M. S. Lam, “Enhancing Software Reliability with Speculative Threads,” Proceedings of the 10th International Conference on Architectural Support for Programming Languages and Operating Systems, 2002, pp. 184–196.
  27. J. D. Collins, D. M. Tullsen, H. Wang, and J. P. Shen, “Dynamic Speculative Precomputation,” Proceedings of the 34th International Symposium on Microarchitecture, 2001, p. 306.
  28. Y. H. Song and M. Dubois, “Assisted Execution,” Technical Report No. CENG 98-25, Department of Electrical Engineering—Systems, University of Southern California, Los Angeles, CA 90089, 1998.
  29. D. Kim, S. S.-W. Liao, P. H. Wang, J. del Cuvillo, X. Tian, X. Zou, H. Wang, D. Yeung, M. Girkar, and J. P. Shen, “Physical Experimentation with Prefetching Helper Threads on Intel's Hyper-Threaded Processors,” Proceedings of the International Symposium on Code Generation and Optimization, 2004, p. 27.
  30. C.-K. Luk, “Tolerating Memory Latency Through Software-Controlled Pre-Execution in Simultaneous Multithreading Processors,” Proceedings of the 28th Annual International Symposium on Computer Architecture, 2001, pp. 40–51.
  31. A. Roth and G. Sohi, “Speculative Data-Driven Multithreading,” Proceedings of the 7th International Symposium on High-Performance Computer Architecture, 2001, pp. 37–48.
  32. Y. Solihin, J. Lee, and J. Torrellas, “Using a User-Level Memory Thread for Correlation Prefetching,” Proceedings of the 29th International Symposium on Computer Architecture, 2002, pp. 171–182.
  33. R. Alverson, D. Callahan, D. Cummings, B. Koblenz, A. Porterfield, and B. Smith, “The Tera Computer System,” Proceedings of the 4th International Conference on Supercomputing, 1990, pp. 1–6.
  34. W. Hillis and L. Tucker, “The CM-5 Connection Machine: A Scalable Supercomputer,” Commun. ACM 36, No. 11, 31–40 (1993).
  35. S. K. Reinhardt, J. R. Larus, and D. A. Wood, “Tempest and Typhoon: User-Level Shared Memory,” Proceedings of the 21st Annual International Symposium on Computer Architecture, 1994; see http://www.eecs.umich.edu/~stever/pubs/isca94_typhoon.pdf.
  36. E. Spertus, S. C. Goldstein, K. E. Schauser, T. von Eicken, D. E. Culler, and W. J. Dally, “Evaluation of Mechanisms for Fine-Grained Parallel Programs in the J-Machine and the CM-5,” Proceedings of the 20th Annual International Symposium on Computer Architecture, 1993; see http://citeseer.csail.mit.edu/cache/papers/cs/1282/http: zSzzSzwww.cs.ucsb.eduzSz~schauserzSzpaperszSz93-isca. pdf/spertus93evaluation.pdf.
  37. W. J. Dally, L. Chao, A. Chein, S. Hassoun, W. Horwat, J. Kaplan, P. Song, B. Totty, and S. Wills, “Architecture of a Message-Driven Processor,” Proceedings of the 14th Annual International Symposium on Computer Architecture, 1987, pp. 189–196.
  38. E. Witchel, J. Cates, and K. Asanovic, “Mondrian Memory Protection,” Proceedings of the 10th International Conference on Architectural Support for Programming Languages and Operating Systems, 2002, pp. 304–315.
  39. SPEC Benchmarks, Standard Performance Evaluation Corporation; see http://www.spec.org.
  40. SESC; see http://sesc.sourceforge.net.


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