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IBM Journal of Research and Development

Exploratory Systems Research   Volume 50, Number 2/3, 2006
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Modeling wire delay, area, power, and performance in a simulation infrastructure - Author Bios

by N. P. Carter
and A. Hussain
Biographical sketches of authors

Nicholas P. Carter University of Illinois at Urbana–Champaign, 1308 W. Main Street, Urbana, Illinois 61801 (npcarter@uiuc.edu). Professor Carter is an Assistant Professor at the University of Illinois at Urbana–Champaign (UIUC). Prior to joining the UIUC in 1999, he was a graduate student at the Massachusetts Institute of Technology, where he was the memory system architect for William J. Dally's M-Machine project. Professor Carter's research interests focus on computer architectures that incorporate devices other than silicon transistors and structures other than conventional microprocessors.

Azmat Hussain Digital Enterprise Group, Intel Corporation, 5200 NE Elam Young Parkway, Hillsboro, Oregon 97124 (azmat.hussain@intel.com). Mr. Hussain received an M.S. degree in electrical engineering from the University of Illinois at Urbana–Champaign. He is currently working in the architecture design group for Intel Corporation.


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