IBM®
Skip to main content
    Country/region [change]    Terms of use
 
 
 
    Home    Products    Services & solutions    Support & downloads    My account    

IBM Journal of Research and Development
Exploratory Systems Research   Volume 50, Number 2/3, 2006
Table of contents: HTMLPDF This article: HTMLPDF   Copyright info

Limited switch dynamic logic circuits for high-speed low-power circuit design - References

 by W. Belluomini,
D. Jamsek,
A. K. Martin,
C. McDowell,
R. K. Montoye,
H. C. Ngo,
and J. Sawada
References

  1. R. H. Krambeck, C. M. Lee, and H. Law, “High-Speed Compact Circuits with CMOS,” IEEE J. Solid-State Circuits 17, No. 3, 614–619 (June 1982).
  2. V. Friedman and S. Liu, “Dynamic Logic CMOS Circuits,” IEEE J. Solid-State Circuits 19, No. 2, 263–266 (April 1984).
  3. L. Heller, W. Griffin, J. Davis, and N. Thoma, “Cascode Voltage Switch Logic: A Differential CMOS Logic Family,” Proceedings of the IEEE International Solid-State Circuits Conference, 1984, pp. 16–17.
  4. C. M. Lee and E. W. Szeto, “Zipper CMOS,” IEEE Circuits & Devices 2, No. 3, 10–17 (May 1986).
  5. F. Murabayashi, H. Yamada, T. Yamauchi, T. Ido, T. Nishiyama, K. Shimamura, S. Tanaka, T. Hotta, T. Shimizu, and H. Sawamoto, “2.5V Novel CMOS Circuit Techniques for a 150MHz Superscalar RISC Processor,” IEEE J. Solid-State Circuits 31, No. 7, 972–980 (July 1996).
  6. T. Thorp, G. Yee, and C. Sechen, “Domino Logic Synthesis Using Complex Static Gates,” Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1998, pp. 242–247.
  7. K. J. Nowka and T. Galambos, “Circuit Design Techniques for a Gigahertz Integer Microprocessor,” International Conference on Computer Design, 1998, pp. 11–16.
  8. J. Pretorius, A. Shubat, and C. Salama, “Latched Domino CMOS Logic,” IEEE J. Solid-State Circuits 21, No. 4, 514–522 (August 1986).
  9. G. Yee and C. Sechen, “Dynamic Logic Synthesis,” Proceedings of the IEEE Custom Integrated Circuits Conference, 1997, pp. 345–348.
  10. W. Belluomini, D. Jamsek, A. Martin, C. McDowell, R. Montoye, T. Nguyen, H. Ngo, J. Sawada, I. Vo, and R. Datta, “An 8GHz Floating-Point Multiply,” Proceedings of the IEEE International Solid-State Circuits Conference, 2005, pp. 374–376.
  11. R. Montoye, W. Belluomini, H. Ngo, C. McDowell, J. Sawada, T. Nguyet, B. Veraa, J. Wagoner, and M. Lee, “A Double Precision Floating Point Multiply,” Proceedings of the IEEE International Solid-State Circuits Conference, 2003, pp. 336–337.
  12. N. Itoh, Y. Naemura, H. Makino, Y. Nakase, T. Yoshihara, and Y. Horiba, “A 600-MHz 54x54-bit Multiplier with Rectangular-Styled Wallace Tree,” IEEE J. Solid-State Circuits 36, No. 2, 249–257 (February 2001).
  13. D. Deleganes, M. Barany, G. Geannopoulos, K. Kreitzer, A. Singh, and S. Wijeratne, “Low-Voltage-Swing Logic Circuits for a 7GHz X86 Integer Core,” Proceedings of the IEEE International Solid-State Circuits Conference, 2004, pp. 336–337.
  14. S. Mathew, M. Anders, B. Bloechel, T. Nguyen, R. Krishnamurthy, and S. Borkar, “A 4-GHz 300-mW 64-bit Integer Execution ALU with Dual Supply Voltages in 90-nm CMOS,” IEEE J. Solid-State Circuits 40, No. 1, 44–51 (January 2005).


    About IBM    Privacy    Contact