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IBM Journal of Research and Development
Exploratory Systems Research   Volume 50, Number 2/3, 2005
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Decomposing the load–store queue by function for power reduction and scalability - References

 by L. Baugh
and C. Zilles
References

  1. A. Roth, “A High-Bandwidth Load-Store Unit for Single- and Multi-Threaded Processors,” Technical Report MS-CIS-04-09, University of Pennsylvania, Philadelphia, PA 19104, 2004.
  2. H. W. Cain and M. H. Lipasti, “Memory Ordering: A Value-Based Approach,” Proceedings of the 31st Annual International Symposium on Computer Architecture, 2004, pp. 90–101.
  3. A. Roth, “Store Vulnerability Window (SVW): Re-Execution Filtering for Enhanced Load Optimization,” Proceedings of the 32nd Annual International Symposium on Computer Architecture, 2005, pp. 458–468.
  4. Il Park, C.-L. Ooi, and T. N. Vijaykumar, “Reducing Design Complexity of the Load-Store Queue,” Proceedings of the 36th Annual IEEE/ACM International Symposium on Microarchitecture, 2003, pp. 411–422.
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  8. E. F. Torres, P. Ibanez, V. Vinals, and J. M. Llaberia, “Store Buffer Design in First-Level Multibanked Data Caches,” Proceedings of the 32nd Annual International Symposium on Computer Architecture, 2005, pp. 469–480.
  9. R. E. Kessler, “The Alpha 21264 Microprocessor,” IEEE Micro 19, No. 2, 24–36 (1999).
  10. M. F. Chowdhury and D. M. Carmean, “Method, Apparatus, and System for Maintaining Processor Ordering by Checking Load Addresses of Unretired Load Instructions Against Snooping Store Addresses,” U.S. Patent Application 6484254, November 2002.
  11. V. Adve, C. Lattner, M. Brukman, A. Shukla, and B. Gaeke, “LLVA: A Low-Level Virtual Instruction Set Architecture,” Proceedings of the 36th Annual IEEE/ACM International Symposium on Microarchitecture, 2003, pp. 205–216.
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  14. A. Klaiber, “The Technology Behind Crusoe Processors,” white paper, Transmeta Corporation, 3990 Freedom Circle, Santa Clara, CA 95054, January 2000.
  15. C. Zilles and G. Sohi, “Master/Slave Speculative Parallelization,” Proceedings of the 35th Annual IEEE/ACM International Symposium on Microarchitecture, 2002, pp. 85–96.
  16. C. N. Keltcher, K. J. McGrath, A. Ahmed, and P. Conway, “The AMD Opteron Processor for Multiprocessor Servers,” IEEE Micro 23, No. 2, 66–76 (2003).
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  18. P. Shivakumar and N. Jouppi, “CACTI 3.0: An Integrated Cache Timing, Power, and Area Model,” Technical Report 2001/2, COMPAQ Western Research Laboratory, Palo Alto, CA 94301, 2001.


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