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IBM Journal of Research and Development
Exploratory Systems Research   Volume 50, Number 2/3, 2006
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Braids and fibers: Language constructs with architectural support for adaptive responses to memory latencies - References

 by D. F. Bacon
and X. Shen
References

  1. W. A. Wulf and S. A. Mckee, “Hitting the Memory Wall: Implications of the Obvious,” Computer Arch. News 23, No. 1, 20–24 (March 1995).
  2. C. May, E. Silha, R. Simpson, and H. Warren, Eds., The PowerPC Architecture: A Specification for a New Family of RISC Processors, Second Edition, Morgan Kaufmann, San Francisco, 1994.
  3. M. Horowitz, M. Martonosi, T. C. Mowry, and M. D. Smith, “Informing Memory Operations: Memory Performance Feedback Mechanisms and Their Applications,” ACM Trans. Computer Syst. 16, No. 2, 170–205 (May 1998).
  4. J. M. Tendler, J. S. Dodson, J. S. Fields, Jr., H. Le, and B. Sinharoy, “POWER4 System Microarchitecture,” IBM J. Res. & Dev. 46, No. 1, 5–25 (January 2002).
  5. J. McCarthy, “Recursive Functions of Symbolic Expressions and Their Computation by Machine,” Commun. ACM 3, No. 4, 184–195 (April 1960).
  6. R. Jones and R. Lins, Garbage Collection, John Wiley and Sons, Ltd., Chichester, England, 1996.
  7. T. C. Mowry and S. R. Ramkissoon, “Software-Controlled Multithreading Using Informing Memory Operations,” Proceedings of the 6th International Symposium on High-Performance Computer Architecture, 2000, pp. 121–132.
  8. D. C. Morris and D. B. Hunt, “Computer System Having an Instruction for Probing Memory Latency,” U.S. Patent No. 6,308,261, October 2001.
  9. D. E. Culler, A. C. Arpaci-Dusseau, S. C. Goldstein, A. Krishnamurthy, S. Lumetta, T. von Eicken, and K. A. Yelick, “Parallel Programming in Split-C,” Proceedings of the International Conference on Supercomputing, November 1993, pp. 262–273.
  10. Arvind, R. S. Nikhil, and K. K. Pingali, “I-Structures: Data Structures for Parallel Computing,” ACM Trans. Programming Lang. & Syst. 11, No. 4, 598–632 (October 1989).
  11. L. Hammond, V. Wong, M. Chen, B. D. Carlstrom, J. D. Davis, B. Hertzberg, M. K. Prabhu, H. Wijaya, C. Kozyrakis, and K. Olukotun, “Transactional Memory Coherence and Consistency,” Proceedings of the 31st International Symposium on Computer Architecture, June 2004, p. 102.


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