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IBM Journal of Research and Development
POWER5 and Packaging   Volume 49, Number 4/5, 2005
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POWER5 system microarchitecture - References

 by B. Sinharoy,
R. N. Kalla,
J. M. Tendler,
R. J. Eickemeyer,
and J. B. Joyner
References

  1. J. M. Tendler, J. S. Dodson, J. S. Fields, Jr., H. Le, and B. Sinharoy, “POWER4 System Microarchitecture,” IBM J. Res. & Dev. 46, No. 1, 5–25 (January 2002).
  2. R. Kalla, B. Sinharoy, and J. M. Tendler, “IBM POWER5 Chip: A Dual-Core Multithreaded Processor,” IEEE Micro 24, No. 2, 40–47 (March–April 2004).
  3. J. M. Borkenhagen, R. J. Eickmeyer, R. N. Kalla, and S. R. Kunkel, “A Multithreaded PowerPC Processor for Commercial Servers,” IBM J. Res. & Dev. 44, No. 6, 885–898 (November 2000).
  4. R. Alverson, D. Callahan, D. Cummings, B. Koblenz, A. Porterfield, and B. Smith, “The Tera Computer System,” presented at the 1990 ACM International Conference on Supercomputing, Amsterdam, Netherlands, June 1990.
  5. D. M. Tullsen, S. J. Eggers, and H. M. Levy, “Simultaneous Multithreading: Maximizing On-Chip Parallelism,” Proceedings of the 22nd Annual International Symposium on Computer Architecture, June 1995, pp. 392–403.
  6. C. May, E. Silha, R. Simpson, and H. Warren, The PowerPC Architecture, Morgan Kaufmann Publishers, San Francisco, 1994.
  7. O. Herescu, B. Olszewski, and H. Hua, “Performance Workloads Characterization on POWER5 with Simultaneous Multi Threading Support,” Proceedings of the Eighth Workshop on Computer Architecture Evaluation Using Commercial Workloads, February 2005, pp. 15–23.
  8. See http://www-1.ibm.com/servers/eserver/pseries/campaigns/chipkill.pdf..
  9. D. Brooks, P. Bose, V. Srinivasan, M. K. Gschwind, P. G. Emma, and M. G. Rosenfield, “New Methodology for Early-Stage, Microarchitecture-Level Power–Performance Analysis of Microprocessors,” IBM J. Res. & Dev. 47, No. 5/6, 653–670 (September/November 2003).
  10. J. Clabes, J. Friedrich, M. Sweet, J. DiLullo, S. Chu, D. Plass, J. Dawson, P. Muench, L. Powell, M. Floyd, B. Sinharoy, M. Lee, M. Goulet, J. Wagoner, N. Schwartz, S. Runyon, G. Gorman, P. Restle, R. Kalla, J. McGill, and S. Dodson, “Design and Implementation of the POWER5 Microprocessor,” ISSCC Digest of Technical Papers, February 2004, pp. 56–57.
  11. D. C. Bossen, A. Kitamorn, K. F. Reick, and M. S. Floyd, “Fault-Tolerant Design of the IBM pSeries 690 System Using POWER4 Processor Technology,” IBM J. Res. & Dev. 46, No. 1, 77–86 (January 2002).


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