Microminiature packaging and integrated circuitry: The work of E. F. Rent, with an application to on-chip interconnection requirements

The introduction and presentation of empirical rules that describe the interconnectivity of computer hardware components first appeared with the publication of a paper by Landman and Russo in 1971 [1]. This publication presented an overview of an empirical relationship understood by members of the IBM computer development groups prior to 1960, when E. F. Rent wrote two internal memoranda that describe his methods and graphical techniques to illustrate the relationship between properties of computer hardware components. The 1971 paper has been referenced extensively in the literature of several scientific fields, including semiconductor circuitry, computer systems, applied mathematics, the applied sciences, and semiconductor manufacturing technology. Specifically, as semiconductor circuitry continues to increase in complexity to ultra-large-scale integrated (ULSI) circuitry, Rent's work has provided guidance for the design and evaluation of ULSI chips and the technologies with which they are manufactured [2, 3]. As an example, researchers have derived theoretical models based on the 1971 interpretation of Rent's work [1, 4] to anticipate properties of future computer systems. In this work, the inputs to the models are empirical parameters that are referred to as Rent parameters.

There remains a need in the literature for the publication of the contents of the two memoranda. We have obtained copies of Rent's memoranda, and one goal of this paper is to present them for the first time within the context of the development of computer hardware components at IBM since the 1950s. To achieve this goal, we present an overview of the two IBM computers that Rent analyzed in the memoranda and a review of computer systems development at IBM from the 1950s to the present. A second goal of this paper is to discuss an interpretation of these memoranda that is suitable for today's computer hardware components, since the components in today's systems differ significantly from those discussed in the original memoranda. This paper also describes an application of this interpretation to the problem of assessing the extent to which estimates provided by existing wire-length distribution models agree with actual wire-length measurements. Here, the desired goal is to obtain improved estimates of wire-length requirements for circuitry on ULSI chips. For this application, we obtained model estimates for wire-length requirements and compared the estimates with measured wire-length requirements in manufactured chips.

This paper is organized as follows. We review the impact of Rent's work, followed by a review of computer systems hardware, including IBM computer systems built since the 1950s and then, more specifically, two systems that Rent discusses in his memoranda. Rent's memoranda on microminiature packaging are then presented. We describe an interpretation of the memoranda that is suitable for today's computer hardware components and then describe an application of this interpretation to existing wire-length distribution models and interconnection requirements, followed by a discussion and presentation of our conclusions.

Rent's work has had a significant impact in a range of scientific fields, and the literature that references the 1971 paper [1] can be broadly arranged into the following scientific areas: interconnections, semiconductor circuitry, computer systems design, applied mathematics, applied sciences, and semiconductor manufacturing technology. The purpose of this section is to provide an overview of the impact of Rent's work and to provide examples of research in each of these areas.

Several interpretations of the 1971 paper exist, including the external interpretation [4–8] and the topological interpretation [8, 9]. According to the external interpretation, the external Rent parameters {k, p} are obtained from the slope and y-intercept of linear fits to log–log plots of the number of input/output pins T_IO as a function of the number of gates N_gates without further partitioning [1, 4–8, 10]. In this interpretation, k represents the Rent coefficient and p represents the Rent exponent. According to the topological interpretation, the topological Rent parameters {k*, p*} are obtained by first partitioning each design hypergraph hierarchically and then extracting the slope and y-intercept from linear fits to log–log plots of the number of terminals as a function of the number of gates, as described in detail in [8–12]. In this interpretation, k* represents the Rent coefficient and p* represents the Rent exponent. Additional information about the external interpretation is described in [4, 5]. The literature that discusses Rent's work prior to the interpretation [13] described in this paper, including references presented in this section, is based on the 1971 interpretation [1].

Table 1 [1, 4, 5, 8, 10, 14] shows values of the Rent parameters—obtained with different interpretations of Rent's work—for several design types. In this table, the values of the Rent coefficient and Rent exponent are shown for block graphs, square arrays, static random access memory (SRAM), gate arrays, chip and module, board and system, microprocessors, application-specific integrated circuit (ASIC)-like control logic, and benchmark circuits. The date of each analysis and design names are also shown. The data in the table shows that the value of the Rent exponent tends to be less than unity for these interpretations. The data also shows that the Rent exponent can take on a range of values from 0.12 to 0.99, and that the Rent coefficient can take on a larger range of values from 0.8 to 82.

To describe the increasing complexity [2] of interconnections in semiconductor circuitry and to estimate the physical and electrical characteristics of chip wiring, researchers have developed models based on the 1971 interpretation of Rent's work. The purpose of this section is to discuss these characteristics, which include on-chip interconnection requirements, performance metrics for interconnections, power dissipation in interconnections, signal fan-out distributions, and interconnection congestion in a design layout.

On-chip interconnection requirements
The earliest application of the 1971 work has been the derivation of interconnection models by Donath [14, 15], Davis et al. [5–7, 16–19], and Christie and Stroobandt [9]. These interconnection models provide estimates for the wire-length distributions, average wire length, and total interconnection length required to wire chip circuitry correctly. These models assume that the designs are square, are completely tiled with square logic gates, have signals with unity fan-out, contain circuitry that is associated only with the logical function of the design, and allocate all of the available space for wire routing. The topological Rent parameters are input into the expressions provided by the Donath models [14, 15] and the Christie model [9], and the external Rent parameters are input into the expressions provided by the Davis model [5–7].

Additional work that describes interconnection requirements in large-scale integration (LSI) and very large-scale integration (VLSI) chips is provided in [10, 20–22]. Methods to extract Rent parameters are discussed in [4, 5, 8, 9, 23–25]. Interconnection requirements have been assessed in microprocessors [4], ASICs [4], memory elements [4], and control logic circuitry in high-performance microprocessors [10]. Interconnection models have also been developed for designs that are rectangular [26], designs that contain signals with multiple fan-out [27, 28], designs that contain one or more blockages [29], field-programmable gate arrays (FPGAs) [30–35], three-dimensional integrated circuits [32, 36–40], and three-dimensional anisotropic systems [41].

Performance metrics
The wiring distributions predicted by the existing wire-length distribution models in the previous section, combined with technology information (such as wire pitch and the number of available metal layers), have been used to obtain interconnection performance metrics such as the one that combines a wire distribution model with a 50% delay model for interconnections from the input of an inverter driver to the output of a inverter receiver, as discussed in [42]. These metrics have helped researchers decide how to optimize wire and inter-layer dielectric characteristics, such as metal thickness and dielectric thickness.

Power dissipation
Models for power dissipation and power estimation that take into account the impact of interconnections have been developed and are described in [43].

Fan-out distributions
Methods to estimate the number of signals with each fan-out in chip designs are described in [28, 44, 45].

Congestion
Methods to estimate interconnection congestion in chip designs are provided in [46, 47].

Researchers have also developed models that are based on Rent's work to partition circuitry and to estimate additional circuitry requirements, such as switching requirements, gate count, and gate area. Bakoglu [4] and Stroobandt [48, 49] provide overviews of research in interconnection requirements in ULSI circuitry. This section provides additional references for these models. Methods to partition circuitry are discussed in [50, 51], switching requirements in circuitry are discussed in [52], and methods to estimate the number of logic gates and the gate area in chips are presented in [53, 54].

The design of computer systems has changed significantly in the past 50 years [2]. Bakoglu [4], Sai-Halasz [55], and Dooijes [56] provide three discussions of trends in computer technology. Researchers in computer systems design have referenced Rent's work in several applications, such as digital information processing, estimation of system-level interconnection requirements, computer architecture, packaging, testing, interconnection requirements in systems-on-chips (SoCs), and system-cost models for evaluating the tradeoff between using off-chip interconnections and increasing chip area and the number of on-chip interconnections. In addition, a research group at the University of California at Los Angeles is collaborating with Hewlett-Packard Company to develop a chemically assembled electronic nanocomputer (CAEN) [57]. The purpose of this section is to present a discussion of some of these applications.

Digital information processing
In the field of digital information processing, Keyes [58–60] references the papers of Landman and Russo [1] in his discussions of the physics of VLSI components.

System-level interconnection requirements
Methods to estimate system-level interconnection requirements are discussed in [22, 52, 61–66]. A series of workshops to present material on the subject of system-level interconnect prediction (SLIP) was established in 1999, and additional information is available online [67].

Computer architecture
Methods to extract Rent parameters from different types of computer architectures are discussed in [24, 25]. The impact of Rent's work on strategies to design massively parallel systems is discussed in [25]. Estimates of the number of memory bits that are required to replace a random logic circuit are discussed in [68]. Additional applications in computer architecture for nanotechnology are discussed in [69].

Packaging
The impact of interconnections on system and packaging requirements is discussed in [4, 22, 55, 56, 70–72]. Interconnection requirements at the interfaces between chips and modules are discussed in [73].

Testing
Methods for chip testing and fault analysis are presented in [74].

SoCs
Design methodologies for SoCs and the associated interconnections, including global signals, clock distributions, and power grids, are discussed in [40].

System-cost models
A system-cost model has been developed [75, 76] to evaluate the tradeoff between using off-chip interconnections and increasing the silicon die area, which increases the number of on-chip interconnections. In this model, there are three cost elements: the cost of processing silicon, the cost of wasted silicon that is unusable after processing, and the cost of assembly. This model assumes that the cost of assembly is proportional to the number of pins on the package, which they obtain from references to Rent's work.

Rent's work has also been discussed in the field of applied mathematics. Mandelbrot discusses this work in his book entitled Fractals: Form, Chance, and Dimension [77]. Ozaktas discusses additional concepts of connectivity for circuit graphs and provides generalizations for systems with a Rent exponent that takes on different values throughout the interconnection hierarchy [78, 79].

Researchers have applied Rent's work to molecular electronics and optics. This section discusses these applications and provides references.

Molecular electronics
Researchers in molecular electronics have developed a cellular FPGA. Inputs to this system include Rent's parameters and information about cellular automata [80]. This work points out that cellular FPGAs differ from traditional FPGAs because they are periodic structures. Cellular FPGAs support only nearest-neighbor connections, rather than interconnections on several metal layers, as is the case for ULSI back-end-of-line chip architectures.

Optics
Rent's work has been applied to an assessment of interconnectivity requirements of free-space optical interconnections, as reported in [81, 82], where brief comparisons with conventional interconnections are provided.

The increasing complexity of today's manufacturing technologies makes it more and more difficult to implement innovations in manufacturing. Although innovations are costly as a result, they do allow us to manufacture chips with desirable characteristics such as higher performance, lower power dissipation, higher circuit density, and higher yield.

Recognizing the need to estimate the impact of these desirable characteristics for each technology, researchers have developed performance models for chips and systems. These models include a cycle-time model [55], SUSPENS [4, 83], AIM [84], GENESYS [85], RIPE [86], BACPAC [87, 88], and GTX [89]. The purpose of this section is to describe briefly the characteristics of three of the models: SUSPENS, BACPAC, and GTX; information about the other models is available in the references listed.

The Stanford University System Performance Simulator (SUSPENS) [4, 83] is a performance model that calculates the maximum clock frequency, chip area, and chip power dissipation as a function of a list of parameters that includes physical constants, Rent's parameters, number of logic gates on the chip, total capacitance of the interconnection per unit length, interconnect pitch, and board-level characteristics.

The Berkeley Advanced Chip Performance Calculator (BACPAC) [87, 88] is a model that calculates characteristics of system-level performance as a function of device characteristics, interconnection characteristics, and system characteristics. The device characteristics include the operating voltage, threshold voltage, gate oxide thickness, and drain current. The interconnection characteristics are the number of metal layers, metal resistivity, and interlayer dielectric constant. The system-level inputs include the design size and Rent's parameters. The outputs of the model are listed in [87] and include chip area, maximum clock frequency, wiring requirements, power dissipation, and projected yield.

The Microelectronics Advanced Research Corporation (MARCO) Gigascale Systems Research Center (GSRC) Technology Extrapolation (GTX) [89] is a system model that calculates system-level performance characteristics such as system cycle time, die size, and power dissipation.

Significant changes have occurred in the development and manufacturing of computer hardware components since 1960, when Rent wrote his two memoranda. The purpose of this section is to review technical hardware innovations in computer hardware components sold in the past five decades and to describe the two computers discussed in Rent's memoranda [90–94].

Throughout much of the 1950s, as indicated in Table 2 [3, 94–98] a key component of IBM computers was the cathode-ray vacuum tube for storage, as well as conventional switching vacuum tubes for logic circuitry; as a result, a single central processing unit (CPU) composed of many of these tubes occupied approximately 90 cubic feet of space. Table 2 lists the IBM systems and the associated innovations in these systems since the 1950s. This table shows that by 1959–1960, vacuum tube technology was superseded by the introduction of discrete transistors in such IBM computers as the 1401 and 1410—the computers that Rent discusses in his memoranda.

In 1964, discrete transistor technology was replaced by hybrid solid logic technology consisting of semiconductor chips, printed wires, and printed resistors. Computer hardware components constructed in hybrid solid logic technology appear in the IBM System/360* computer.

In 1980, IBM introduced the 3081 system. This system introduced the packaging concept of a thermal conduction module (TCM) to the marketplace. The design of the TCM … was driven by partitioning and wiring considerations influenced by Mr. Rent's work before semiconductor technology was able to contain an entire high-performance CPU on a single chip.¹

Figure 6 in the paper by Seraphim and Feinberg [3] shows a planar board of the 3081 system, and it is stated there that the TCMs plug directly into the printed circuit back panel. A review of the evolution of electronic packaging in IBM from the early 1960s through 1981 is presented in [3].

In 1985, IBM introduced its first mainframe with memory chips containing one million bits each, as indicated in Table 2. By 1990, each memory chip in the RISC System/6000 contained four million bits.

In 2001, IBM introduced computer systems based on the POWER4* chip that contained two CPUs, approximately 174 million transistors, and more than one mile of copper wiring on a penny-sized 4-cm² silicon chip [95], thereby realizing a significant volume reduction compared with the early 1950s CPU.

In 2004, IBM introduced two computer systems. The eServer z990 contains 121 million transistors, and the eServer i5 550 contains 276 million transistors.

The 1401 [Figure 1(a)] was introduced in the marketplace on October 5, 1959, and was sold for nearly 12 years, until February 8, 1971. Composed entirely of discrete transistors, the main components of the IBM 1401 were a 1401 processing unit, 1402 card reader–punch, and 1403 printer. It was the first computer to sell more than 10,000 units [90, 91]. According to the IBM Corporate Archives [90], the system performs functions previously requiring a number of separate machines: card reading and punching, separation of output cards, calculating, and printing. Within the 1401 system itself, the IBM 1401 processing unit controls the entire system by means of its stored program. It performs the arithmetic and logical functions, controls card reading and punching, magnetic tape input and output, and tells the printer what to print and where to print it [90]. Regarding speed, the press datasheet reported that in one minute, the 1401 Processing Unit can perform 193,300 additions (eight-digit numbers) or 25,000 multiplications (six-digit numbers by four-digit numbers) [90].

Figure 1

The 1410 [Figure 1(b)] was introduced in the marketplace on September 12, 1960, and was sold for nearly ten years, until March 30, 1970 [92]. It was offered in three basic configurations, with an optional paper tape reader and magnetic character reader [92, 93]. These configurations are the following:

• IBM 1410 Data Processing Card System: This configuration was a high-speed flexible system containing large-volume storage facilities and fast input/output units for up-to-the-minute, accurate punched card output and printed reports [92]. It consisted of a 1402 card reader–punch, 1403 printer, 1411 processing unit, 1414 input/output synchronizer, and 1415 console.
• IBM 1410 Data Processing Tape System: This configuration added to the speed and efficiency of the 1410 card system with high-volume storage capacities and increased data input/output speeds [92]. Magnetic tape units were available with this system.
• IBM RAMAC 1410 Data Processing System: This configuration provided mammoth disk storage facilities for the IBM 1410 Data Processing Systems, [and] consisted of the 1410 card system, with or without the tape units [92]. The configuration also included disk storage.

The previous section has presented a review of the computer hardware systems environment that existed in 1960 when Rent wrote his memoranda. The purpose of this section is to present the two memoranda within the context of this environment. In the memoranda, Rent describes his analysis of the IBM 1401 and 1410 computer systems and describes his method to deduce an empirical relationship between the properties of the hardware components in these systems. The first memorandum is shown in Appendix A on pages 784–788. This memorandum discusses the 1410 and is dated November 28, 1960. The second memorandum is shown in Appendix B on pages 789–791. This memorandum discusses the 1401 and the 1410 and is dated December 12, 1960.

Appendix A: First Rent memorandum—November 28, 1960

Page 784
Page 785
Page 786
Page 787
Page 788

Appendix B: Second Rent memorandum—December 12, 1960

Page 789
Page 790
Page 791

The 1401 and 1410 hardware components that Rent discusses in the memoranda are the computer chassis, card, circuit count, and edge connector count. The computer chassis contains several cards that are connected in the chassis. Each card is composed of one or more circuits; the circuits on the card are either used circuits or unused circuits. The term used circuit refers to a circuit that is connected and performs some function; the term unused circuit refers to a circuit that exists yet is not required. The purpose of edge connectors is to connect used circuits on a card with other used circuits located on other cards within the chassis. A circuit is also referred to as a logic block. Photographs of a card and the wiring on the back of a chassis are shown in Figure 2. In the earlier memo, Rent describes his method to obtain the circuit count and edge connector count of the cards on each chassis of the 1410 computer system as follows: The circuit count was made by card type and then a count of one given for each of the following: 2 way logic block, 3 way logic block, emitter follower, indicator driver, power inverter, line driver etc. No count was made for diode clamp cards or resistor load cards. All unused circuits on cards were removed from the count to give an actual logic circuit count for each chassis. The net edge connector count required a total for all edge connectors on a chassis less, (1) those connectors that were used to feed signals across a chassis and not go to any logic on the chassis and (2) those connectors that were used to distribute to the adjacent chassis signals that were developed on the chassis.

Figure 2

On pages 787 and 791 are Rent's plots of the circuit count per card as a function of the number of edge connectors per card on log–log graph paper. Rent also calculated the average block-to-edge-connector ratio, which is shown in another log–log plot on page 788. He wrote in the memorandum (page 784), Therefore, the average of the three control chassis will be considered as more typical of all chassis and will be used as the reference point in further discussions. On pages 787 and 791, the ordinate is labeled logic blocks/card, and the abscissa is labeled signal pins/card. Each of these plots contains several data points added by hand, where the data points are the number of logic blocks and number of edge connectors obtained according to the descriptions quoted above. A solid line is drawn by hand through several data points in these plots, and Rent pays particular attention to the solid line that connects the point labeled C1 with the point labeled single card unit logic (IO pins) (see page 785 for a discussion and a listing of the points that Rent identifies on the line). An inspection of this line indicates that it may be described by the expression,

where y represents the log of the ordinate and x represents the log of the abscissa, and where we obtain m = 1.49, b = −0.94 for the line drawn on the plot. This expression may be rearranged as

where m´ = 0.67 and b´ = 0.63, and also as the expression,

where b´ = log(B´), x = log(X), y = log(Y). Y represents the ordinate, and X represents the abscissa.

In the second memo, Rent performs his analysis on the 1401 computer system and considers four separate chassis labeled 01A7, 01A8, 01B1, and 01B2 in the memo. The plot of the data obtained for these four chassis is shown on page 791, which is a log–log plot similar to that on page 787, but with the addition of this new data. Note that a solid line also connects the two datapoints C1 and single card unit logic (IO pins) in the plot of page 791, and that the locations of the datapoints A7, A8, B1, and B2 are identified on the plot. In this later memo, Rent writes (page 789) that It should be noted that these chassis points are quite scattered on the graph but still they fall between the curve for compact cards and the curve derived from 1410 chassis counts, and that These chassis counts verify that the curve drawn from the 1410 counts when used would not pin limit the mother board, which indicates that the results in the first memo are verified by the results in the second memo.

Figure 3(a), prepared by the authors of this paper, is a schematic representation of a computer hardware chassis and the computer components described in the memoranda. The chassis shown in the figure contains six cards; three cards are used (A, B, C), and three cards are unused (D, E, F). Specifically, card A is a representation of the card shown in Figure 2(a), and the chassis is a representation of the chassis shown in Figure 2(b). In Figure 3(a), the dashed curved lines between the two chassis represent that these connections are excluded in Rent's calculations.

Figure 3

Based on the previous section, the personal knowledge of one of us (R. A. Rand) of the 1401 and 1410 computers, and our experience with the design and analysis of ULSI circuitry for high-performance microprocessors [10, 99, 100], we have derived an historically equivalent interpretation of Rent's memoranda that is suitable for today's computer components. In this paper, the phrase historically equivalent refers to our mapping of each component described by Rent in the phrases for circuit count and edge connector count, as provided in the previous section, to a functionally equivalent component that exists in today's circuitry [13].

Figure 3(b) shows a schematic representation of today's computer circuitry. In Design A, shown in the figure, all inputs have unity fan-out, the used signals are labeled with notation {s₁, …, s₉}, and the used gates are labeled with notation {g₁, …, g₄}.

For today's designs, the historically equivalent terms for chassis and card are functional unit and design, respectively. The historically equivalent term for the building block, or circuit, is logic gate. The historically equivalent term for circuit count is gate count, which can be represented by the term N_gates, a quantity that describes the number of gates in a design. An expression for N_gates can be written according to the expression

where the term N_all represents the total number of gates in a design, the term N_unconnected represents the number of unconnected gates, the term N_spare represents the number of gates associated with spare logic, the term N_filler represents the number of filler cells, and the term N_decap represents the number of decoupling capacitors. To ensure an accurate count of N_gates, it is important to itemize carefully the contributions to the four terms N_unconnected, N_spare, N_filler, N_decap in Equation (4). These four terms do not contribute to the number of functional gates in a design, although they may exist for various reasons [13].

The historically equivalent term for edge connector count is used connection, which can be represented with the term N_conn and can be written [13] as

(5)

where the sum is taken over the signal nets N_nets, F_i represents the fan-out of each signal net, T_IO represents the number of input pins and output pins in the design [5], and the total fan-out, F_total, is given by the expression

In Equation (5), the term (F_i + 1) represents the total number of connections made by a single signal net in a design; each signal net has a single driver and can have fan-out F_i ≥ 1. Note that Equation (5) implicitly contains information about design complexity through the dependence of the historically equivalent Rent parameters k_R and p_R on the average fan-out f, which can be written as f = F_total/N_nets, since values for the Rent parameters {k_R, p_R} are obtained through least-square linear fits to log–log plots of N_conn as a function of N_gates.

For the case of Design A in Figure 3(b), the value of N_gates = 4. The value for N_conn is obtained with Equations (4) and (5), where N_gates = 4, F_total = 10, N_nets = 9, and T_IO = 7. Substituting these values into Equation (5), we obtain the number of connections for Design A as N_conn,A = 12, as can be verified by a direct count of the connections in Design A. Additional examples of designs with inputs that have multiple fan-outs and designs that are partitioned into several subdesigns are given in [13].

A second method of obtaining the number of connections N_conn in a design is to count the number of gates N_j of each logic type j, such as the inverter (inv) and nand2. The total number of connections N_conn can also be written according to the expression,

(6)

where n_conn,j represents the number of connections of gates of type j, and where the sum is taken over all of the gate types G in a design. Note that the total number of gates N_gates can be written as the expression

(7)

Examples of the number of connections per gate n_conn,j are shown in Figure 4. The number of connections for a gate type j can be calculated by taking the sum of the number of inputs n_i and the number of outputs n_o, such that n_conn,j = n_i + n_o.

Figure 4

As an example, we consider the case of Design A shown in Figure 3(b). Design A contains three types of logic gates: inv, nand2, and nand4. From Figure 4, we see that each inv contributes two connections, each nand2 contributes three connections, and each nand4 contributes five connections. With these substitutions, Equation (6) takes the form for the number of connections for Design A, N_conn,A, as the expression

Next, Figure 3(b) shows that the number of inv is N_inv = 2, the number of nand2 is N_nand2 = 1, and the number of nand4 is N_nand4 = 1. Substituting these values into Equation (8), we obtain N_conn,A = 12, which is the same value previously obtained with Equation (5), as described above.

Additional examples for Designs F, F1, F2, and F3 in [13] are shown in Table 3 [13]. This table shows the value for N_conn and the allocation of gates in each design for each of the different gate types: inv, nand2, nand4, nor2, and2, and or2. Equation (6) can be evaluated for each design, with Figure 4, to obtain the expressions for each design:

In this paper, the parameters k_R and p_R represent the inverse log of the intercept and the slope, respectively, of a linear fit to N_conn as a function of N_gates in a log–log plot, according to the expression

which can also be expressed as

(14)

Each datapoint in such a plot is generated from one design within a functional unit, and the series of datapoints considered for a fit according to Equation (14) is generated from the set of all designs within the unit.

An inspection of Equation (6) shows that N_conn tends to increase linearly with N_gates for 1) the case in which each design in a set of designs is composed of the same type of gate, 2) the case in which each design in a set of designs contains the same allocation of gates, and 3) the case in which one gate type is the primary constituent of all of the designs in the group. For example, consider a set of designs {a, b, c} in which all of the designs are composed of a different number of nand2 gates. For these designs, the number of connections can be written in a straightforward fashion as the expressions

where the terms N_conn,a, N_conn,b, and N_conn,c represent the number of connections in designs a, b, and c, respectively, and the term N_nand2 represents the number of nand2. A plot of these three datapoints would produce an exponent with value p_R = 1.

As a second example, consider a set of designs {d, e, f} in which all of the designs contain the same proportion of gates, such as 80% inv, 15% nand2, and 5% nand4 gates, or 30% inv, 30% nand2, and 40% nor2. For the first example of these designs, the number of connections can be written as the expressions,

where the term N_gates represents the total number of gates. An inspection of the expressions in Equations (18)–(20) shows that they can be written in the same form as Equations (15)–(17), as shown on the right-hand side of the expressions above. The expressions also show that, for these designs, the number of connections increases linearly with the number of gates; for this case, it is expected that the exponent has value p_R = 1 and that the uncertainty in the value of the exponent is zero.

For the cases in which other sets of designs contain similar allocation of gates in each design, it is expected that the exponent will also tend to approximate unity, with p_R ~ 1 with a low value of uncertainty in the value of p_R. For other cases in which the designs contain disparate allocations of gates in each design, it is expected that the expressions for the number of connections in each design will take on a more complicated relationship for the designs; for these cases, the value of the exponent is obtained from the log–log plot, and it is expected that the uncertainty in the value of the exponent will increase.

This section presents an application of the interpretation of microminiature packaging described in the previous section to the problem of interconnection requirements in ULSI circuitry [13]. The designs selected for this study are all of the control logic designs in the IBM POWER4 core [95]. Here, the goal is to obtain improved estimates of wire-length requirements for circuitry on ULSI chips. A discussion of the limitations of these wiring estimates and a comparison with prior work are presented in [13].

For each design, estimates and ranges for the normalized probability density function p_int(L), cumulative distribution function P(L), average wire length L_avg(p_R), and total wire length L_tot(p_R) are obtained. To obtain these estimates, we first extract values for the parameters {k_R, p_R} for the designs in each functional unit with Equation (13). As discussed in an earlier section, each design provides one datapoint on the log–log plot for each functional unit; for this datapoint, the value for N_gates takes into careful account the values of N_all, N_unconnected, N_spare, N_filler, and N_decap, and the value of N_conn is obtained from a count of F_total, N_nets, and T_IO.

Figure 5 shows a log–log plot of N_conn as a function of N_gates for each of the six units in the POWER4 core. For example, in this figure, the 18 datapoints for the IFU are provided by the 18 individual designs in the IFU. Linear fits of the design data to Equation (13) for each unit provide the appropriate values of {k_R, p_R}, where the value of k_R falls roughly in the range of 1 to 4, as shown in Table 4 [10] and p_R ~ 1. Complete listings of the estimates and ranges within one standard deviation for k_R and p_R are given in [13]. For comparison, Table 4 also lists the values of the Rent parameters {k, p} that are obtained with the external interpretation of Rent's memoranda [1, 5–8, 10]. The results in Table 4 show that the value of p_R is close to unity for each of the six functional units in the core, which suggests that the number of connections in all of the designs in the core tends to increase linearly with the number of gates. Since these designs are composed mainly of inv, the choices of gates in all of the designs are generated with the same set of sophisticated computer-aided design (CAD) software programs, and since it has been observed that designs that contain both one type of gate and a similar gate allocation are expected to exhibit a linear dependence of the number of connections as a function of the number of gates, as discussed in a previous section, it is expected that p_R ~ 1.

Figure 5

Table 5 [5] compares the values of the average wire-length estimates L_ave(p_R) obtained with the Davis model [5] for each design with the measured average wire length L_a and with the prior estimate L_ave(p) for the control logic designs in the POWER4 IFU. Table 4 compares the total wire-length estimate L_T(p_R) for each design with the measured total wire length L_T and with the prior estimate L_T(p), where L_T(p_R) and L_T(p) are given by the expressions,

where the term N_nets represents the number of connected nets in the design. Table 4 compares estimates of the total wire length L_tot(p_R) in the entire POWER4 core with the measured requirement and with the prior estimate L_tot(p), where L_tot(p_R) and L_tot(p) are given by the expressions,

(22)

where the sums are taken over all control logic designs N_designs in each unit, L^j_avg(p_R) represents the average wire length provided for design j by the Davis model [5] as a function of p_R, L^j_avg(p) represents the average wire-length estimate for design j provided by the Davis model evaluated as a function of p, and N^j_nets represents the number of connected nets in design j.

The results presented in Tables 4 and 5 show that the estimates obtained by evaluating the expressions in the models as functions of {k_R, p_R} show improved agreement with the real wire-length requirements compared with the agreement obtained with prior estimates [10]. Note that the estimates are within 10% of L_T for the IFU. Wire-length estimates are also improved [10, 13] for the designs in the other five units; specifically, wire-length estimates are improved for 13 of 18 IFU designs, all 12 FPU designs, 3 of 4 FXU designs, 10 of 18 IDU designs, 14 of 16 ISU designs, and 28 of 32 LSU designs, compared with prior work.

Table 4 shows that when all of the designs in the POWER4 core are considered as a group, the wire-length estimate for the interconnection requirement in the core is within 30% of the measured requirement. This result also compares favorably with the result obtained in prior work in which agreement between the estimate of total wire length is within 58% of the total wire-length measurement [10].

We now discuss the wire-length requirements for one design, i9, in the IFU. The area occupancy [100] of the design is 74%, which is near the median occupancy of all of the IFU designs; here the term area occupancy refers to the ratio of the area occupied by the used gates to the total area allocated to the design in the silicon die, as described in [100]. Figure 6 shows a histogram of the area occupancy of all 18 IFU designs. The area occupancy of the IFU designs ranges from 28% to 85%, with a mean occupancy of 65%.

Figure 6

Figure 7 compares measurements and estimates of the normalized probability density function p_int(L) and cumulative distribution function P(L) for design i9. In this figure, the estimates are provided by the Davis model [5–7] as functions of the parameter pairs {k, p} and {k_R, p_R}, where the measured values of p_int(L) are shown with solid circles and the measured values of P(L) are shown with hollow squares. The dotted lines indicate distributions that are obtained by evaluating the Davis model as functions of {k, p} [10], and where the upper range and lower range are obtained with the values for the ranges of k and p. The solid lines indicate the distributions that are obtained by evaluating the Davis model as functions of the historically equivalent Rent parameters {k_R, p_R}. The figure shows that the curves obtained with {k_R, p_R} exhibit qualitatively better agreement with the measured curves compared with the curves obtained with parameter pair {k, p} [10].

Figure 7

The approach presented in this paper is intended to provide information for future research and additional applications of Rent's work. To date, Rent's work has been referenced in research and development of a variety of scientific and technical fields, including the following: on-chip interconnections, semiconductor circuitry, computer systems design, applied sciences, and semiconductor manufacturing technology. Examples of applications in each of these fields were provided in an earlier section of this paper. With Rent's work now available in the literature, one is able to study the original sources within the context of the development of computer hardware components. Because prior work was based on the 1971 interpretation of the two Rent memoranda and because significant changes have occurred in the development of computer systems hardware since Rent wrote the two memoranda in 1960, it is necessary to provide an interpretation of these memoranda that is suitable for today's ULSI circuitry.

For the example of on-chip interconnections in ULSI circuitry described in this paper, this approach provides chip designers with techniques to obtain wire-length estimates and distributions that exhibit improved agreement with measured interconnection requirements. These methods help achieve the goal of buildable and functional chip designs in spite of increasingly severe chip-design constraints that include the following: restrictive real-estate specifications, the limited number of metal layers available in the manufacturing technology, aggressive operating frequencies, and power dissipation limits [4, 42, 48, 49, 61–63, 70].

In principle, the development of an interpretation of the memoranda that is applicable for today's ULSI circuitry is essentially the development of a technique to describe more generally the connectivity of nanoscale components, of which integrated circuitry is one specific example. This paper has presented a description of the connectivity of nanoscale components in the silicon brain, where the term silicon brain refers to the high-performance central processing unit (CPU) that contains the specific chip designs examined in this study. Note that this interpretation does not concern itself with the two-dimensional nature of chip layouts, since this constraint is imposed by the current manufacturing processes. Thus, the interpretation of connectivity presented in this paper can, in principle, be applied to descriptions of connectivity in other complex systems; these systems include, for example, the connectivity in the human brain [101–104].

Considered as a complex circuit, the design of the human brain can be described as a network of neurons in conjunction with chemicals that enable a progression of electrical signals and chemical signals to connect the appropriate set of neurons. One may relate the components of the silicon brain and the human brain with the following mapping: The term circuit is understood to be the logic gate in the silicon brain and the neuron in the human brain; the term interconnection is understood to be the wire in the silicon brain and axons in the human brain; the signal inputs are the logic gate inputs in the silicon brain and dendrites in the human brain; the signal outputs are the logic gate outputs in the silicon brain and axon synaptic knobs in the human brain. Specifically, the interpretation for nanoscale components described in this paper provides a technique to quantify the connectivity in the human brain at the neuron level, for example to quantify differences among different brain regions and to distinguish different stages of development, aging, and disease that occur as the result of neural degradation, such as Alzheimer's disease, for which the underlying cause remains unknown at this time.

In this example, this mapping suggests that values of the Rent parameters to quantify the connectivity of components in each region of the human brain can be obtained with the following steps: First, the neurons in one region of the brain are grouped into subregions of neurons; second, a count is obtained of the number of dendrites and axon synaptic knobs and the number of neurons in each subregion; third, the number of potential connections (sum of the number of dendrites and axon synaptic knobs) is plotted on a log–log plot as a function of the number of neurons for each subregion; fourth, a least-square linear fit is made to the graphed data, and the empirical values of the Rent parameters can be extracted from the fit parameters, where the value of the Rent exponent is the value of the slope of the line, and the value of the Rent coefficient is the value of the inverse log of the intercept. Cox–Golgi preparations may provide one technique to visualize these components (neurons, axons, and dendrites) [101–104]. One may use values of the Rent parameters in each region of a normal human brain as a basis for comparison with the corresponding region in other human brains to establish baselines for and quantify the progression of different stages of development, aging, and disease.

To provide background for the extensive body of research based on a 1971 interpretation of the work of E. F. Rent and to satisfy requests from researchers for these memoranda, this paper presents the original work of Rent and an historically equivalent interpretation of these memoranda that is suitable for today's computer hardware components. The interpretation that we introduce for today's computer components is needed because computer components have changed significantly compared with the discrete-transistor-based hardware components that are considered in Rent's original work. This paper also applies this interpretation to existing on-chip wire-length distribution models and presents estimates of interconnection requirements that demonstrate improved agreement to within 30% with actual wire-length requirements compared with prior methods, which obtained agreement with measurements to within 58%.

We thank the reviewers, whose comments have helped to improve this paper substantially. We thank Bernard Landman of the IBM Thomas J. Watson Research Center, Hawthorne, NY, for providing us with copies of E. F. Rent's two memoranda, which were given to him by