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IBM Journal of Research and Development
POWER5 and Packaging   Volume 49, Number 4/5, 2005
Table of contents: HTMLPDF This article: HTMLPDF   Copyright info

Introduction to the Cell multiprocessor - References

 by J. A. Kahle,
M. N. Day,
H. P. Hofstee,
C. R. Johns,
T. R. Maeurer,
and D. Shippy
References

  1. K. Kutaragi, M. Suzuoki, T. Hiroi, H. Magoshi, S. Okamoto, M. Oka, A. Ohba, Y. Yamamoto, M. Furuhashi, M. Tanaka, T. Yutaka, T. Okada, M. Nagamatsu, Y. Urakawa, M. Funyu, A. Kunimatsu, H. Goto, K. Hashimoto, N. Ide, H. Murakami, Y. Ohtaguro, and A. Aono, “A Micro Processor with a 128b CPU, 10 Floating-Point MACs, 4 Floating-Point Dividers, and an MPEG2 Decoder,” ISSCC Digest of Technical Papers, February 1999, pp. 256–257.
  2. A. Kunimatsu, N. Ide, T. Sato, Y. Endo, H. Murakami, T. Kamei, M. Hirano, F. Ishihara, H. Tago, M. Oka, A. Ohba, T. Yutaka, T. Okada, and M. Suzuoki, “Vector Unit Architecture for Emotion Synthesis,” IEEE Micro 20, No. 2, 40–47 (March–April 2000).
  3. H. S. Yang, R. Malik, S. Narasimha, Y. Li, R. Divakaruni, P. Agnello, S. Allen, A. Antreasyan, J. C. Arnold, K. Bandy, M. Belyansky, A. Bonnoit, G. Bronner, V. Chan, X. Chen, Z. Chen, D. Chidambarrao, A. Chou, W. Clark, S. W. Crowder, B. Engel, H. Harifuchi, S. F. Huang, R. Jagannathan, F. F. Jamin, Y. Kohyama, H. Kuroda, C. W. Lai, H. K. Lee, W.-H. Lee, E. H. Lim, W. Lai, A. Mallikarjunan, K. Matsumoto, A. McKnight, J. Nayak, H. Y. Ng, S. Panda, R. Rengarajan, M. Steigerwalt, S. Subbanna, K. Subramanian, J. Sudijono, G. Sudo, S.-P. Sun, B. Tessier, Y. Toyoshima, P. Tran, R. Wise, R. Wong, I. Y. Yang, C. H. Wann, L. T. Su, M. Horstmann, Th. Feudel, A. Wei, K. Frohberg, G. Burbach, M. Gerhardt, M. Lenski, R. Stephan, K. Wieczorek, M. Schaller, H. Salz, J. Hohage, H. Ruelke, J. Klais, P. Huebler, S. Luning, R. van Bentum, G. Grasshoff, C. Schwan, E. Ehrichs, S. Goad, J. Buller, S. Krishnan, D. Greenlaw, M. Raab, and N. Kepler, “Dual Stress Liner for High Performance Sub-45-nm Gate Length SOI CMOS Manufacturing,” Proceedings of the 2004 IEEE International Electron Devices Meeting, December 2004, pp. 1075–1078.
  4. Power Architecture Version 2.02; see http://www-106.ibm.com/developerworks/eserver/library/es-archguide-v2.html.
  5. W. Wulf and S. McKee, “Hitting the Memory Wall: Implications of the Obvious,” ACM Computer Architecture News 23, No. 1, 20–24 (March 1995).
  6. U. Ghoshal and R. Schmidt, “Refrigeration Technologies for Sub-Ambient Temperature Operation of Computing Systems,” ISSCC Digest of Technical Papers, February 2000, pp. 216–217.
  7. R. D. Isaac, “The Future of CMOS Technology,” IBM J. Res. & Dev. 44, No. 3, 369–378 (May 2000).
  8. H. Peter Hofstee, “Power Efficient Processor Architecture and the Cell Processor,” Proceedings of the 11th Conference on High Performance Computing Architectures, February 2005, pp. 258–262.
  9. V. Srinivasan, D. Brooks, M. Gschwind, P. Bose, V. Zyuban, P. N. Strenski, and P. G. Emma, “Optimizing Pipelines for Power and Performance,” Conference Proceedings of the 35th Annual IEEE/ACM International Symposium on Microarchitecture, 2002, pp. 333–344.
  10. See http://www-306.ibm.com/chips/techlib/techlib.nsf/products/Cell.
  11. B. Flachs, S. Asano, S. H. Dhong, H. P. Hofstee, G. Gervais, R. Kim, T. Le, P. Liu, J. Leenstra, J. Liberty, B. Michael, H.-J. Oh, S. M. Mueller, O. Takahashi, A. Hatakeyama, Y. Watanabe, and N. Yano, “The Microarchitecture of the Streaming Processor for a CELL Processor,” Proceedings of the IEEE International Solid-State Circuits Symposium, February 2005, pp. 184–185.
  12. C. J. Anderson, J. Petrovick, J. M. Keaty, J. Warnock, G. Nussbaum, J. M. Tendler, C. Carter, S. Chu, J. Clabes, J. DiLullo, P. Dudley, P. Harvey, B. Krauter, J. LeBlanc, P.-F. Lu, B. McCredie, G. Plum, P. J. Restle, S. Runyon, M. Scheuermann, S. Schmidt, J. Wagoner, R. Weiss, S. Weitzel, and B. Zoric, “Physical Design of a Fourth-Generation POWER GHz Microprocessor,” ISSCC Digest of Technical Papers, February 2001, pp. 232–233.
  13. J. Clabes, J. Friedrich, M. Sweet, J. DiLullo, S. Chu, D. Plass, J. Dawson, P. Muench, L. Powell, M. Floyd, B. Sinharoy, M. Lee, M. Goulet, J. Wagoner, N. Schwartz, S. Runyon, G. Gorman, P. Restle, R. Kalla, J. McGill, and S. Dodson, “Design and Implementation of the POWER5 Microprocessor,” Proceedings of the 41st Design Automation Conference, 2004, pp. 670–672.
  14. T. Asano, T. Nakazato, S. Dhong, A. Kawasumi, J. Silberman, O. Takahashi, M. White, and H. Yoshihara, “A 4.8GHz Fully Pipelined Embedded SRAM in the Streaming Processor of a CELL Processor,” Proceedings of the IEEE International Solid-State Circuits Symposium, February 2005, pp. 486–487.
  15. See http://www.rambus.com/products/xdr/.
  16. K. Chang, S. Pamarti, K. Kaviani, E. Alon, X. Shi, T. Chin, J. Shen, G. Yip, C. Madden, R. Schmitt, C. Yuan, F. Assaderaghi, and M. Horowitz, “Clocking and Circuit Design for a Parallel I/O on a First Generation CELL Processor,” Proceedings of the IEEE International Solid-State Circuits Symposium, February 2005, pp. 526–527.
  17. D. Pham, S. Asano, M. Bolliger, M. N. Day, H. P. Hofstee, C. Johns, J. Kahle, A. Kameyama, J. Keaty, Y. Masubuchi, M. Riley, D. Shippy, D. Stasiak, M. Suzuoki, M. Wang, J. Warnock, S. Weitzel, D. Wendel, T. Yamazaki, and K. Yazawa, “The Design and Implementation of a First-Generation CELL Processor,” Proceedings of the Custom Integrated Circuits Conference, September 2005; to appear.


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