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Volume 48, Number 3/4, 2004
IBM eServer z990 |
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Table of contents:
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This article:
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First- and second-level packaging of the z990 processor cage - References
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by
T.-M. Winkel, W. D. Becker, H. Harrer, H. Pross, D. Kaller, B. Garben, B. J. Chamberlin, and S. A. Kuppinger
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References
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H. Harrer, H. Pross, T.-M. Winkel, W. D. Becker, H. I. Stoller, M. Yamamoto, S. Abe, B. J. Chamberlin, and G. A. Katopis, “First- and Second-Level Packaging for the IBM eServer z900,” IBM J. Res. & Dev. 46, No. 4/5, 397–420 (July/September 2002).
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J. S. Corbin, C. N. Ramirez, and D. E. Massey, “Land Grid Array Sockets for Server Applications,” IBM J. Res. & Dev. 46, No. 6, 763–778 (November 2002).
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G. F. Goth, D. J. Kearney, U. Meyer, and D. W. Porter, “Hybrid Cooling with Cycle Steering in the IBM eServer z990,” IBM J. Res. & Dev. 48, No. 3/4, 409–423 (May/July 2004, this issue).
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J. C. Parrilla, F. E. Bosco, J. S. Corbin, J. Loparco, P. J. Singh, and J. G. Torok, “Packaging the IBM eServer z990 Central Electronic Complex,” IBM J. Res. & Dev. 48, No. 3/4, 395–407 (May/July 2004, this issue).
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G. A. Katopis, W. D. Becker, T. R. Mazzawy, H. H. Smith, C. K. Vakirtzis, S. A. Kuppinger, B. Singh, P. C. Lin, J. Bartells, Jr., G. V. Kihlmire, P. N. Venkatachalam, H. I. Stoller, and J. L. Frankel, “MCM Technology and Design for the S/390 G5 System,” IBM J. Res. & Dev. 43, No. 5/6, 621–650 (September/November 1999).
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P. Singh, S. J. Ahladas, W. D. Becker, F. E. Bosco, J. P. Corrado, G. F. Goth, S. Iruvanti, M. A. Nobile, B. D. Notohardjono, J. H. Quick, E. J. Seminaro, K. M. Soohoo, and C. Wu, “A Power, Packaging, and Cooling Overview of the IBM eServer z900,” IBM J. Res. & Dev. 46, No. 6, 711–738 (November 2002).
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J. U. Knickerbocker, F. L. Pompeo, A. F. Tai, D. L. Thomas, R. D. Weekly, M. G. Nealon, H. C. Hamel, A. Haridass, J. N. Humenik, R. A. Shelleman, S. N. Reddy, K. M. Prettyman, B. V. Fasano, S. K. Ray, T. E. Lombardi, K. C. Marston, P. A. Coico, P. J. Brofman, L. S. Goldmann, D. L. Edwards, J. A. Zitz, S. Iruvanti, S. L. Shinde, and H. P. Longworth, “An Advanced Multichip Module (MCM) for High-Performance UNIX Servers,” IBM J. Res. & Dev. 46, No. 6, 779–804 (November 2002).
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E. Cordero, F. Ferriaolo, M. Floyd, K. Grower, and B. McCredie, “A Synchronous Wave-Pipeline Interface for POWER4,” presented at the IEEE Computer Society HOT CHIPS Workshop, Stanford University, California, August 15-17, 1999.
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P. Mak, M. A. Blake, K. W. Kark, V. K. Papazova, A. E. Seigler, G. E. Strait, G. A. Van Huben, L. Wang, and G. C. Wellwood, “Processor Subsystem Interconnect Architecture for a Large Symmetric Multiprocessing System,” IBM J. Res. & Dev. 48, No. 3/4, 323–337 (May/July 2004, this issue).
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Z. Chen, W. D. Becker, and G. Katopis, “A Fast Simulation Method for Single and Coupled Lossy Lines with Frequency-Dependent Parameters Based on Triangle Impulse Responses,” Proceedings of the 8th IEEE Topical Meeting on Electrical Performance of Electronic Packaging, San Diego, October 25-27, 1999, pp. 257–260.
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Sigrity, Inc., SPEED2000, available online at http://www.sigrity.com/.
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B. Garben, G. A. Katopis, and W. D. Becker, “Package and Chip Design Optimization for Mid-Frequency Power Noise Decoupling,” Proceedings of the 11th IEEE Topical Meeting on Electrical Performance on Electronic Packaging, Monterey, CA, 2002, pp. 245–248.
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