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Volume 48, Number 3/4, 2004
IBM eServer z990 |
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Table of contents:
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This article:
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Accelerating system integration by enhancing hardware, firmware, and co-simulation - References
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by
K.-D. Schubert, E. C. McCain, H. Pape, K. Rebmann, P. M. West, and R. Winkelmann
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References
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F. Baitinger, H. Elfering, G. Kreissig, D. Metz, J. Saalmueller, and F. Scholz, “System Control Structure of the IBM eServer z900,” IBM J. Res. & Dev. 46, No. 4/5, 523–535 (July/September 2002).
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P. Mak, M. A. Blake, C. C. Jones, G. E. Strait, and P. R. Turgeon, “Shared-Cache Clusters in a System with a Fully Shared Memory,” IBM J. Res. & Dev. 41, No. 4/5, 429–448 (July/September 1997).
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P. Mak, G. E. Strait, M. A. Blake, K. W. Kark, V. K. Papazova, A. E. Seigler, G. A. Van Huben, L. Wang, and G. C. Wellwood, “Processor Subsystem Interconnect Architecture for a Large Symmetric Multiprocessing System,” IBM J. Res. & Dev. 48, No. 3/4, 323–337 (May/July 2004, this issue).
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M. Stetter, J. von Buttlar, D. Chan, D. Decker, H. Elfering, P. Gioquindo, T. Hess, S. Koerner, A. Kohler, H. Lindner, K. Petri, and M. Zee, “IBM eServer z990 Improvements in Firmware Simulation,” IBM J. Res. & Dev. 48, No. 3/4, 583–594 (May/July 2004, this issue).
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J. von Buttlar, H. Böhm, R. Ernst, A. Horsch, A. Kohler, H. Schein, M. Stetter, and K. Theurich, “z/CECSIM: An Efficient and Comprehensive Microcode Simulator for the IBM eServer z900,” IBM J. Res. & Dev. 46, No. 4/5, 607–615 (July/September 2002).
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G. Doettling, K. J. Getzlaff, B. Leppla, W. Lipponer, T. Pflueger, T. Schlipf, D. Schmunkamp, and U. Wille, “S/390 Parallel Enterprise Server Generation 3: A Balanced System and Cache Structure,” IBM J. Res. & Dev. 41, No. 4/5, 405–428 (July/September 1997).
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S. Koerner, M. Kuenzel, and E. C. McCain, “IBM eServer z900 System Microcode Verification by Simulation: The Virtual Power-On Process,” IBM J. Res. & Dev. 46, No. 4/5, 587–595 (July/September 2002).
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J. Kayser, S. Koerner, and K.-D. Schubert, “Hyper-Acceleration and HW/SW Co-Verification as an Essential Part of IBM eServer z900 Verification,” IBM J. Res. & Dev. 46, No. 4/5, 597–605 (July/September 2002).
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S. Koerner and S. M. Licker, “Run-Control and Service Element Code Simulation for the S/390 Microprocessor,” IBM J. Res. & Dev. 41, No. 4/5, 577–580 (July/September 1997).
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Gary A. Van Huben, “The Role of Two-Cycle Simulation in the S/390 Verification Process,” IBM J. Res. & Dev. 41, No. 4/5, 593–599 (July/September 1997).
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E. C. McCain, “Post Initial Microcode Load Co-Simulation Method System, and Program Product,” U.S. Patent Reference No. POU920040001US1, filed May 11, 2004.
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D. F. Ackerman, M. H. Decker, J. J. Gosselin, K. M. Lasko, M. P. Mullen, R. E. Rosa, E. V. Valera, and B. Wile, “Simulation of IBM Enterprise System/9000 Models 820 and 900,” IBM J. Res. & Dev. 36, No. 4, 751–764 (July 1992).
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IBM Corporation, z/Architecture Principles of Operation (SA22-7832); see http://www.elink.ibmlink.ibm.com/public/applications/publications/cgibin/pbi.cgi/.
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