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Volume 48, Number 3/4, 2004
IBM eServer z990 |
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Table of contents:
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This article:
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Functional verification of a frequency-programmable switch chip with asynchronous clock sections - References
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by
B. Hoppe, B. Arthur-Mensah, E. W. Chencinski, S. Joseph, H. Kumar, and J. F. Silverio
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References
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D. J. Stigliani, Jr., T. E. Bubb, D. F. Casper, J. H. Chin, S. G. Glassen, J. M. Hoke, V. A. Minassian, J. H. Quick, and C. H. Whitehead, “IBM eServer z900 I/O Subsystem,” IBM J. Res. & Dev. 46, No. 4/5, 421–445 (July/September 2002).
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E. W. Chencinski,
M. J. Becht, T. E. Bubb, C. G. Burwick, J. Haess, M. M. Helms, J. M. Hoke, T. Schlipf, J. M. Turner, H. Ulland, M. H. Walz, C. H. Whitehead, and G. Zilles, “The Structure of Chips and Links Comprising the IBM eServer z990 I/O Subsystem,” IBM J. Res. & Dev. 48, No. 3/4, 449–459 (May/July 2004, this issue).
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C. L. Rao, G. M. King, and B. A. Weiler, “Integrated Cluster Bus Performance for the IBM S/390 Parallel Sysplex,” IBM J. Res. & Dev. 43, No. 5/6, 855–862 (September/November 1999).
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J. M. Hoke, P. W. Bond, R. R. Livolsi, T. C. Lo, F. S. Pidala, and G. Steinbrueck, “Self-Timed Interface of the Input/Output Subsystem of the IBM eServer z900,” IBM J. Res. & Dev. 46, No. 4/5, 447–460 (July/September 2002).
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J. Darringer, E. Davidson, D. Hathaway, B. Koenemann, M. Lavin, B. Lee, J. Morrell, S. Ponnapalli, K. Rahmat, W. Roesner, E. Schanzenbach, and L. Trevillyan, “EDA in IBM: Past, Present and Future,” IEEE Trans. Computer-Aided Design, Integrated Circuits & Syst. 19, 1476–1497 (December 2000).
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B. Wile, M. P. Mullen, C. Hanson, D. G. Bair, K. M. Lasko, P. J. Duffy, E. J. Kaminski, Jr., T. E. Gilbert, S. M. Licker, R. G. Sheldon, W. D. Wollyung, W. J. Lewis, and R. J. Adkins, “Functional Verification of the CMOS S/390 Parallel Enterprise Server G4 System,” IBM J. Res. & Dev. 41, No. 4/5, 549–566 (July/September 1997).
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J. M. Ludden, W. Roesner, G. M. Heiling, J. R. Reysa, J. R. Jackson, B.-L. Chu, M. L. Behm, J. R. Baumgartner, R. D. Peterson, J. Abdulhafiz, W. E. Bucy, J. H. Klaus, D. J. Klema, T. N. Le, F. D. Lewis, P. E. Milling, L. A. McConville, B. S. Nelson, V. Paruthi, T. W. Pouarz, A. D. Romonosky, J. Stuecheli, K. D. Thompson, D. W. Victor, and B. Wile, “Functional Verification of the POWER4 Microprocessor and POWER4 Multiprocessor Systems,” IBM J. Res. & Dev. 46, No. 1, 53–76 (January 2002).
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B. L. Keller and T. J. Snethen, “Built-In Self-Test Support in the IBM Engineering Design System,” IBM J. Res. & Dev. 34, No. 2/3, 406–415 (March/May 1990).
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P. S. Gillis, T. S. Guzowski, B. L. Keller, and R. H. Kerr, “Test Methodologies and Design Automation for IBM ASICs,” IBM J. Res. & Dev. 40, No. 4, 461–474 (July 1996).
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L. Stok, D. S. Kung, D. Brand, A. D. Drumm, A. J. Sullivan, L. N. Reddy, N. Hieter, D. J. Geiger, H. H. Chao, and P. J. Osler, “BooleDozer: Logic Synthesis for ASICs,” IBM J. Res. & Dev. 40, No. 4, 407–430 (July 1996).
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G. A. Van Huben, T. G. McNamara, and T. E. Gilbert, “PLL Modeling and Verification in a Cycle-Simulation Environment,” IBM J. Res. & Dev. 43, No. 5/6, 915–925 (September/November 1999).
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G. G. Hallock, E. J. Kaminski, Jr., K. M. Lasko, and M. P. Mullen, “SimAPI—A Common Programming Interface for Simulation,” IBM J. Res. & Dev. 41, No. 4/5, 601–610 (July/September 1997).
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A. Kuehlmann, A. Srinivasan, and D. P. LaPotin, “Verity—A Formal Verification Program for Custom CMOS Circuits,” IBM J. Res. & Dev. 39, 149–165 (January/March 1995).
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J. Silverio, H. Kumar, S. Joseph, and B. Hoppe, “Method for Verification of Various Asynchronous Frequency Domains in a STI Switch Chip, by Implementing a Greatest Common Factor Mathematical Approach to Generate the Discrete Simulation Cycle Values and Randomly Select the Simulation Cycle Percent Variation Across the Multiple Domains,” patent filed 2003.
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