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IBM Journal of Research and Development 
Volume 48, Number 3/4, 2004
IBM eServer z990
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The IBM eServer z990 floating-point unit - References
by G. Gerwig, H. Wetter, E. M. Schwarz, J. Haess, C. A. Krygowski, B. M. Fleischer, and M. Kroener

References

  1. T. J. Slegel, E. Pfeffer, and J. A. Magee, “The IBM eServer z990 Microprocessor,” IBM J. Res. & Dev.48, No. 3/4, 295–309 (May/July 2004, this issue).
  2. “IEEE Standard for Binary Floating-Point Arithmetic,” ANSI/IEEE Standard 754-1985, The Institute of Electrical and Electronics Engineers, Inc., New York, August 1985.
  3. IBM Corporation, Enterprise Systems Architecture/390 Principles of Operation (SA22-7201); see http://www.elink.ibmlink.ibm.com/public/applications/publications/cgibin/pbi.cgi/.
  4. G. Gerwig and M. Kroener, “Floating-Point-Unit in Standard Cell Design with 116 Bit Wide Dataflow,” Proceedings of the 14th IEEE Symposium on Computer Arithmetic, Adelaide, Australia, April 1999, pp. 266–273.
  5. E. M. Schwarz, L. Sigal, and T. J. McPherson, “CMOS Floating-Point Unit for the S/390 Parallel Enterprise Server G4,” IBM J. Res. & Dev. 41, No. 4/5, 475–488 (July/September 1997).
  6. E. M. Schwarz, R. M. Averill III, and L. J. Sigal, “A Radix-8 CMOS S/390 Multiplier,” Proceedings of the 13th IEEE Symposium on Computer Arithmetic (ARITH '97), Asilomar, CA, July 1997, pp. 2–9.
  7. E. M. Schwarz and C. A. Krygowski, “The S/390 G5 Floating-Point Unit,” IBM J. Res. & Dev. 43, No. 5/6, 707–721 (September/November 1999).
  8. E. M. Schwarz, R. M. Smith, and C. A. Krygowski, “The S/390 G5 Floating Point Unit Supporting Hex and Binary Architectures,” Proceedings of the 14th IEEE Symposium on Computer Arithmetic, Adelaide, Australia, April 1999, pp. 258–265.
  9. E. M. Schwarz, M. A. Check, C.-L. K. Shum, T. Koehler, S. B. Swaney, J. D. MacDougall, and C. A. Krygowski, “The Microarchitecture of the IBM eServer z900 Processor,” IBM J. Res. & Dev. 46, No. 4/5, 381–395 (July/September 2002).
  10. G. Gerwig, H. Wetter, E. M. Schwarz, and J. Haess, “High Performance Floating-Point Unit with 116 Bit Wide Divider,” Proceedings of the 16th Symposium on Computer Arithmetic, Santiago de Compostela, Spain, June 2003, pp. 87–94.
  11. K. D. Tocher, “Techniques of Multiplication and Division for Automatic Binary Computers,” Quart. J. Mech. Appl. Math. 11, Pt. 3, 364–384 (1958).
  12. J. E. Robertson, “A New Class of Digital Division Methods,” IRE Trans. Electronic Computers EC-7, 218–222 (September 1958).
  13. IBM Corporation, z/Architecture Principles of Operation (SA22-7832); see http://www.elink.ibmlink.ibm.com/public/applications/publications/cgibin/pbi.cgi/.
  14. C. A. Krygowski and E. M. Schwarz, “Floating-Point Multiplier for De-Normalized Inputs,” U.S. Patent Application No. 2002/0124037 A1, p. 8, September 5, 2002.
  15. E. M. Schwarz, M. Schmookler, and S. D. Trong, “Hardware Implementations of Denormalized Numbers,” Proceedings of the 16th Symposium on Computer Arithmetic, Santiago de Compostela, Spain, June 2003, pp. 70–78.
  16. M. D. Ercegovac and T. Lang, Division and Square Root: Digit-Recurrence Algorithms and Implementations, Kluwer Academic Publishers, Boston, 1994.
  17. D. L. Harris, S. F. Oberman, and M. A. Horowitz, “SRT Division Architectures and Implementations,” Proceedings of the 13th IEEE Symposium on Computer Arithmetic, Asilomar, CA, July 1997, pp. 18–25.
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