Biographical sketches of authors

Edward W. Chencinski IBM Systems and Technology Group, 2455 South Road, Poughkeepsie, New York 12601 (chencins@us.ibm.com). Mr. Chencinski received a B.S. degree in electrical engineering from Lehigh University in 1980, joining IBM that same year. He was involved in the ES/3090 SCE and expanded storage hardware design, as well as the logic support element design of the ES/9000. In the early 1990s Mr. Chencinski joined the G3/G4 CMOS cryptographic hardware processor design team, focusing on pervasive functions, simulation, timing, and modular exponentiation. He is currently a Senior Engineer leading the STI switch chip design team.

Michael J. Becht IBM Systems and Technology Group, 2455 South Road, Poughkeepsie, New York 12601 (becht@us.ibm.com). Mr. Becht is a Staff Engineer in the IBM eServer I/O Hardware Development group. He received his B.S. degree in electrical engineering from the University of Delaware in 1998. That same year he joined IBM in Poughkeepsie, New York, where he was involved in the development of the SP switch for pSeries supercomputers. Since then he has held various technical positions and is currently engaged in the development of next-generation I/O for zSeries supercomputers.

Tim E. Bubb IBM Systems and Technology Group, 2455 South Road, Poughkeepsie, New York 12601 (bubb@us.ibm.com). Mr. Bubb is an Advisory Engineer in the IBM eServer I/O Hardware Development group. He received his B.S. degree in electrical engineering from the Virginia Polytechnic Institute in 1988, and his M.S. degree from Purdue University in 1989. He joined IBM at Poughkeepsie, New York, in 1990 and has held various technical and management positions in the eServer I/O design area. Mr. Bubb has received an IBM Outstanding Innovation Award for his work on the Hydra I/O subsystem, and he has received two IBM Outstanding Technical Achievement Awards for his work on the Multiprise 3000 and IBM eServer z900 I/O subsystems.

Carolynn G. Burwick IBM Systems and Technology Group, 2455 South Road, Poughkeepsie, New York 12601 (burwick@us.ibm.com). Ms. Burwick is a Staff Engineer in the IBM eServer I/O Hardware Development group. She received her B.S. degree in computer engineering from the Rochester Institute of Technology in 1997. She joined IBM in Poughkeepsie, New York, the following year and has held various technical positions in the eServer I/O area. Ms. Burwick is currently engaged in the development of next-generation I/O for zSeries supercomputers.

Juergen Haess IBM Systems and Technology Group, IBM Deutschland Entwicklung GmbH, Schoenaicherstrasse 220, 71032 Boeblingen, Germany (haess@de.ibm.com). Mr. Haess received his M.S. degree in electrical engineering from the University of Karlsruhe, Germany, in 1980; since joining IBM, he has worked on I/O adapter development for many years and for several released products. In 1994 he moved to Poughkeepsie for half a year to transfer the design of the G3, STI-based FIB chip to Poughkeepsie and to coordinate its design and bringup with Boeblingen. During various jobs he has received an IBM division award, an IBM team award, and three IBM Invention Achievement Awards for his work. In 1997 he joined the CPU development team, where he became a member of the FPU team in 1999. To support the Sweep design, he joined the I/O team to adapt the FIB design. He currently works in floating-point design for next-generation IBM pSeries and zSeries processors. Mr. Haess is an author or coauthor of eight patents and thirteen publications, including a conference proceeding and two journal articles.

Markus M. Helms IBM Systems and Technology Group, IBM Deutschland Entwicklung GmbH, Schoenaicherstrasse 220, 71032 Boeblingen, Germany (helms@de.ibm.com). Mr. Helms studied electrical engineering at the Berufsakademie Stuttgart and received the Dipl.Ing. degree in 1993, joining the IBM laboratories in Boeblingen that same year as an R&D engineer. He worked in various technical positions (verification, logic design, architecture) in the zSeries I/O Adapter area. Most of his time was spent on development of the MBA. His current focus in the InfiniBand I/O Architecture and its common design implementation for the IBM eServer. Mr. Helms has received an IBM Outstanding Technical Achievement Award, an IBM Invention Achievement Award, and numerous informal awards.

Joseph M. Hoke IBM Systems and Technology Group, 2455 South Road, Poughkeepsie, New York 12601 (jmhoke@us.ibm.com). Mr. Hoke is an Advisory Engineer in the IBM eServer I/O Hardware Development group. He received the B.S. degree in electrical engineering from the University of Illinois at Chicago in 1987 and continued his studies under a university fellowship, receiving the M.S. degree in electrical engineering from Northwestern University in 1989. He joined IBM at Poughkeepsie, New York, in 1989 and has held various technical positions in the eServer I/O area. Mr. Hoke holds several patents used in the IBM ESCON and Sysplex products, and he has received two IBM Invention Achievement Awards. He has received an IBM Outstanding Technical Achievement Award for his work on ESCON and his work on the G5 Server, and another for his contributions to the eServer zSeries.

Thomas Schlipf IBM Systems and Technology Group, IBM Deutschland Entwicklung GmbH, Schoenaicherstrasse 220, 71032 Boeblingen, Germany (schlipf@de.ibm.com). Mr. Schlipf is a Senior Technical Staff Member in the IBM Systems and Technology Group. He received his M.S.E.E. degree from the University of Karlsruhe, Germany, in 1983. In 1985, after working for a time at the Robert Bosch Company, Germany, he joined the IBM Server Group development laboratories in Boeblingen. Since then he has worked on the hardware design of I/O chips. He has led three MBA projects and has received an IBM Outstanding Innovation Award, an IBM Outstanding Technical Achievement Award, and two IBM Invention Achievement Awards. Mr. Schlipf is a member of the IEEE.

Jeffrey M. Turner IBM Systems and Technology Group, 2455 South Road, Poughkeepsie, New York 12601 (turner@us.ibm.com). Mr. Turner received a B.Eng. degree in electrical engineering from Rensselaer Polytechnic Institute in 1978 and an M.Eng. degree in 1979. In 1979 he joined IBM in East Fishkill, New York. He has held various technical positions in embedded systems, memory controller, and I/O subsystem design, and has received IBM Outstanding Innovation and Outstanding Technical Achievement Awards for his work on the zSeries Open Systems Adapter. Mr. Turner is currently a Senior Technical Staff Member in the eServer I/O area.

Hartmut Ulland IBM Systems and Technology Group, IBM Deutschland Entwicklung GmbH, Schoenaicherstrasse 220, 71032 Boeblingen, Germany (hulland@de.ibm.com). Mr. Ulland received his M.S. degree (Dipl.Ing.) in electrical engineering from the Technical University (RWTH) Aachen in 1969 and joined the IBM Boeblingen laboratory, where he worked on various System/370-oriented projects in the Advanced Technology Department. From 1982 to 1985 he was on assignment to Boca Raton, Florida, where he led the design of the I/O connection for a RISC-based system. Since 1986 Mr. Ulland has served as a logic designer and/or team leader in S/390 I/O and PU-related projects. He has served as the team leader of the Sweep design since 2001, and has received two IBM Invention Achievement Awards.

Manfred H. Walz IBM Systems and Technology Group, IBM Deutschland Entwicklung GmbH, Schoenaicherstrasse 220, 71032 Boeblingen, Germany (mhwalz@de.ibm.com). Mr. Walz received the Dipl.Ing. degree in electrical engineering from the Berufsakademie Stuttgart in 1979. In 1979 he joined the IBM development laboratories in Boeblingen, working on memory for the 43XX systems. From 1985 to 1995 Mr. Walz led several memory development projects. In 1996 he joined the I/O subsystem development team. He has led the MBA development for two generations of the zSeries Systems. Mr. Walz has served as a lecturer at the Berufsakademie Stuttgart; he is a member of the IEEE.

Carl H. Whitehead IBM Systems and Technology Group, 2455 South Road, Poughkeepsie, New York 12601 (whitehea@us.ibm.com). Mr. Whitehead is a Senior Engineer in the eServer I/O Hardware Development group. He received a B.S. degree in electrical engineering from Manhattan College in 1979. He subsequently joined IBM at Poughkeepsie, New York, and has held various technical positions in the eServer processor and I/O areas. Mr. Whitehead has received three IBM Outstanding Technical Achievement Awards for his contributions to several generations of zSeries I/O subsystems.

Gerhard Zilles IBM Systems and Technology Group, IBM Deutschland Entwicklung GmbH, Schoenaicherstrasse 220, 71032 Boeblingen, Germany (zilles@de.ibm.com). Mr. Zilles studied information technique at the Fachhochschule Jülich. In 1978, after some practical experience at the nuclear research center in Jülich, he joined the IBM Laboratory in Boeblingen, working for ten years on storage controller and memory card hardware design. Since 1988 he has worked on various I/O chip designs as engineer/team leader, and has worked for a year on sysplex firmware development. Recently he has been involved in the EETR and Sweep projects.