Biographical sketches of authors

Dean G. Bair IBM Systems and Technology Group, 522 South Road, Poughkeepsie, New York 12601 (dgbair@us.ibm.com). Mr. Bair, a Senior Software Engineer, joined IBM in 1984. He received his B.S. degree in electrical engineering from the State University of New York at New Paltz in 1998. He has worked in the field of verification for 18 years and has verified multiple design points including I/O controllers, shared L2 cache designs, and microprocessors. Mr. Bair was the verification team leader for the z990 superscalar multibook microprocessor complex, as well as previous generations of zSeries machines. He has received numerous awards, including multiple IBM Outstanding Innovation Awards, and patents for his efforts in the field of verification. Mr. Bair is currently working on verifying future Systems and Technology Group design points.

Steven M. German IBM Research Division, IBM Thomas J. Watson Research Center, P.O. Box 218, Yorktown Heights, New York 10598 (german@watson.ibm.com). Dr. German received his A.B. and Ph.D. degrees in applied mathematics from Harvard University in 1974 and 1981, respectively. He has more than 25 years of experience in many aspects of formal methods. In the 1970s, he developed the first automated system for proving the absence of common run-time errors in computer programs. After joining IBM in 1995, he originated a new field of verification algorithms for checking processor pipelines. Recently, he has focused on verification of multiprocessor memory protocols. Dr. German pioneered the Formal Design approach for developing hardware protocols, in which formal verification is integrated into the design process. He led the project to formally verify the memory protocol for the zSeries server and is currently verifying its successors.

William D. Wollyung IBM Systems and Technology Group, 2455 South Road, Poughkeepsie, New York 12601 (wollyung@us.ibm.com). Mr. Wollyung is an Advisory Engineer. He joined IBM in 1974 and has been in verification since 1983. He received a B.S. degree in computer science from Lasalle University in 1998. He has worked on processor, storage controller, I/O, and memory verification, and is currently working on memory controller verification. Mr. Wollyung received a Gold Level Quality Award for his work in 9121 simulation, and IBM Outstanding Technical Achievement Awards for his work on 3090 S verification, S/390 G4 processor verification, and S/390 G5 storage subsystem development. He also received an IBM Outstanding Contribution Award for the G6 opera server development.

Edward J. Kaminski, Jr. IBM Systems and Technology Group, 2455 South Road, Poughkeepsie, New York 12601 (ekamin01@us.ibm.com). Mr. Kaminski, a Senior Verification Engineer at the IBM Poughkeepsie facility, received his B.S. degree in electrical engineering from the Rensselaer Polytechnic Institute in 1987. He joined IBM at Poughkeepsie in 1987, working on symmetric multiprocessor (SMP) storage subsystem verification for the 3090 H2 design; he has continued in verification through subsequent generations of SMP designs to the current zSeries servers. Mr. Kaminski has received multiple awards for verification work, including an IBM Outstanding Technical Achievement Award.

James Schafer IBM Systems and Technology Group, 2455 South Road, Poughkeepsie, New York 12601 (schafer@us.ibm.com). Mr. Schafer received a B.S. degree from Purdue University in 1982, joining IBM that same year. For his first eleven years with IBM, he worked on logic product diagnostic systems in East Fishkill, where he published several papers and received his first IBM Outstanding Technical Achievement Award. His functional verification career began in 1993 in Austin, working on various PowerPC support chips. Mr. Schafer started with the S/390 Server Group in 1996, and is currently a Senior Engineer working as team leader for system controller element verification. He has received multiple awards for his zSeries verification work, including an IBM Outstanding Innovation Award and an IBM Outstanding Technical Achievement Award.

Michael P. Mullen IBM Systems and Technology Group, 522 South Road, Poughkeepsie, New York 12601 (mpmullen@us.ibm.com). Mr. Mullen is currently a Senior Programmer. He received a B.S. degree in computer science from Union College in 1976, joining IBM that same year, and an M.S. degree in computer/information sciences from Syracuse University in 1981. Mr. Mullen has worked on the development of many mainframe systems; he is currently responsible for the hardware design verification of IBM z/Series processors. He has received several IBM Outstanding Technical Achievement Awards for his work in microcode development, the AVPGEN system, and hardware verification.

William J. Lewis IBM Systems and Technology Group, 2455 South Road, Poughkeepsie, New York 12601 (wjlewis@us.ibm.com). Mr. Lewis joined IBM in 1982 and is currently a Senior Engineer. He received a B.A. degree in computer science from the State University of New York at Oswego. After starting out in the hardware performance area, he has worked in design verification since 1985. Mr. Lewis has received IBM Outstanding Technical Achievement Awards for G4 and G5 processor verification, and an IBM Outstanding Innovation Award for zSeries verification.

Rebecca Wisniewski IBM Systems and Technology Group, 2455 South Road, Poughkeepsie, New York 12601 (wisnski@us.ibm.com). Ms. Wisniewski joined IBM in 1982 after receiving a B.S. degree in computer science from the College of Engineering, University of Illinois at Urbana– Champaign. She started in the hardware performance area, focusing on processor performance. In 1993, she began working in simulation on scalable POWERparallel adapters and switches. Since 1998 she has been doing buffer control element (BCE) unit simulation and is currently the zSeries processor verification leader. Ms. Wisniewski has received an IBM Outstanding Innovation Award for her work on z9000 verification.

Joerg Walter IBM Systems and Technology Group, IBM Deutschland Entwicklung GmbH, Schoenaicherstrasse 220, 71032 Boeblingen, Germany (jwalter@de.ibm.com). Dr. Walter received his diploma in electrical engineering in 1986 and his Ph.D. in computer science in 1993, both from the University of Stuttgart, Germany. He joined IBM in Boeblingen in 1993, working on memory card verification for the S/390 Parallel Enterprise Server G3. Dr. Walter is currently the verification team leader for the Boeblingen zSeries processor verification group.

Steven Mittermaier IBM Systems and Technology Group, 2455 South Road, Poughkeepsie, New York 12601 (mitt@us.ibm.com). Mr. Mittermaier received an A.A.S. degree in electrical engineering from the University of Toledo in 1988, and a B.S. degree in electrical engineering in 1996 from the State University of New York at New Paltz. He joined IBM in 1988, working on photolithographic tools and support in semiconductor production. He later joined the CEC verification group in Poughkeepsie, working on processor simulation and becoming an expert on cross- product coverage. Mr. Mittermaier is currently working on processor verification and coverage for future Systems and Technology Group products.

Visda Vokhshoori IBM Systems and Technology Group, 2455 South Road, Poughkeepsie, New York 12601 (visda@us.ibm.com). Ms. Vokhshoori received a B.S. degree in electrical engineering from the State University of New York at New Paltz in 1998, and an M.S. degree in electrical engineering from Columbia University in 2002. She joined the IBM z/OS component test group in 1998 as a consultant. In 2001 Ms. Vokhshoori joined the hardware verification group, where she is engaged in various verification projects with a concentration in functional coverage verification.

Robert J. Adkins IBM Systems and Technology Group, 2455 South Road, Poughkeepsie, New York 12601 (adkins@us.ibm.com). Mr. Adkins is an Advisory Software Engineer. He has been in verification since 1985 and has worked on both processor and storage controller verification for multiple Server Group systems. He has received IBM Outstanding Technical Achievement Awards for his work on ES/9000 CP element simulation, S/390 G4 processor verification, and S/390 G5 storage subsystem development, and an IBM Outstanding Contribution Award for his work on S/390 G6 opera server development. Mr. Adkins currently works on the verification of future Systems and Technology Group microprocessors.

Michael Halas IBM Systems and Technology Group, 2455 South Road, Poughkeepsie, New York 12603 (mohalas@us.ibm.com). Mr. Halas received a B.S. degree in electrical/computer engineering from Rutgers University in 2001. He worked at Compaq Computer as a co-op student in 2000 on Tru64 UNIX clustering software and at IBM as an intern in 2001, joining the company as a full-time employee in 2002. He has worked on random verification of the BCE and a z990 I/O adapter chip. Mr. Halas is a verification engineer currently working on verification of the system controller for future Systems and Technology Group projects.

Thomas Ruane IBM Systems and Technology Group, 2455 South Road, Poughkeepsie, New York 12601 (ruane@us.ibm.com). Mr. Ruane received a B.A. degree in English from the State University of New York at New Paltz in 1976 and an M.S. degree in computer science from Union College in 1980, joining IBM that same year. He is currently working on element simulation and tool support for follow-on z990 systems.

Ursel Hahn IBM Systems and Technology Group, IBM Deutschland Entwicklung GmbH, Schoenaicherstrasse 220, 71032 Boeblingen, Germany (hahnurs@de.ibm.com). Mrs. Hahn is currently an engineer in the IBM Server Group. She joined IBM in 1977 and is currently working on coverage, element simulation, and AVPGEN for follow-on z990 systems.