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IBM Journal of Research and Development 
Volume 48, Number 3/4, 2004
IBM eServer z990
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Configurable system simulation model build comprising packaging design data - References
by H.-W. Anderson, H. Kriese, W. Roesner, and K.-D. Schubert

References

  1. H. Kohler, “Design of a Multichip Module Containing a 12Way S/390 Microprocessor Subsystem,” presented at the Ninth Annual IEEE International ASIC Conference, 1996.
  2. J. M. Ludden, W. Roesner, G. M. Heiling, J. R. Reysa, J. R. Jackson, B.-L. Chu, M. L. Behm, J. R. Baumgartner, R. D. Peterson, J. Abdulhafiz, W. E. Bucy, J. H. Klaus, D. J. Klema, T. N. Le, F. D. Lewis, P. E. Milling, L. A. McConville, B. S. Nelson, V. Paruthi, T. W. Pouarz, A. D. Romonosky, J. Stuecheli, K. D. Thompson, D. W. Victor, and B. Wile, “Functional Verification of the POWER4 Microprocessor and POWER4 Multiprocessor Systems,” IBM J. Res. & Dev. 46, No. 1, 53–76 (January 2002).
  3. IEEE Standard VHDL Language Reference Manual, IEEE STD 1076-1993, IEEE Press, New York, 1993.
  4. The Chip Hierarchical Design System Technical Data Standard; see http://www.si2.org/index_files/si2_publications.htm#CHDStdThe_Chip_Hierarchical_Design/.
  5. J. Darringer, E. Davidson, D. Hathaway, B. Koenemann, M. Lavin, J. Morrell, K. Rahmat, W. Roesner, E. Schanzenbach, G. Tellez, and L. Trevillyan, “EDA in IBM: Past, Present and Future,” IEEE Trans. Computer-Aided Design 19, No. 12, 1476–1497 (December 2000).
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