1. Introduction

Silicon–germanium (SiGe) BiCMOS technology, which achieved its first manufacturing qualification in 1996, is now in its fourth lithographic generation of development. This class of technology integrates high-performance heterojunction bipolar transistors (HBTs) with state-of-the-art CMOS technology. Key technology characteristics for the four generations have been reported by IBM [1–4]. All generations of BiCMOS technology are compatible with an associated IBM CMOS technology in devices, metallization (interconnects), and ASIC design system. Figure 1 is a SiGe BiCMOS chart showing the evolution of performance and minimum lithographic feature size together with some derivative technologies. As shown in Figure 2, the HBT cutoff frequency f_T has improved from 47 GHz in the 0.5-µm generation to 210 GHz in the 0.13-µm generation. The pace of development continues unabated, and there are no apparent barriers to scaling the SiGe HBTs beyond 210 GHz.

Figure 1   Figure 2

The SiGe HBT performance has been significantly improved by a combination of vertical and lateral scaling. Structural improvements included shrinking the emitter width and reducing layer thicknesses for the first three generations and migrating to a new raised extrinsic base (RXB) structure for the 0.13-µm generation. Vertical profile scaling included increasing the drift field by increasing the Ge concentration and reducing the graded base width, adding carbon (C) to decrease diffusion, reducing the thickness of the collector epitaxial layer, and minimizing the emitter thermal cycle. In the 0.13-µm generation, vertical and lateral profile scaling has led to a reduction in the parasitics of the HBT, especially in the base, collector, and emitter resistances (R_B, R_C, R_E) and total collector–base capacitance (C_CB). Coupled with the increased f_T, this reduction in parasitics is expected to lead to an increased f_max (the maximum frequency of oscillation of a device, often referred to as U, for unilateral matched power gain, or MAG, for maximum available gain) in the devices. All devices in the production technologies must pass stringent quality and reliability tests [5]. Both the 120-GHz and 210-GHz technologies exhibit collector–emitter breakdown voltage with base open circuit (BV_CEO) values around 2 V, but this is not a serious concern, because in typical circuits the base is biased through a finite resistance and the true HBT breakdown voltage is between BV_CER and BV_CES (typically between 3.5 V and 6.5 V. It is more important to know the safe operation area and how large signal parameters vary as a function of use condition [6, 7].

In contrast to the trickle of early circuits [8], there is now a flood of new SiGe products in almost every wired and wireless application area. A sample of the wide variety of SiGe BiCMOS circuits illustrates the wide-ranging applicability of these technologies (Table 1).

Table 1   Circuits demonstrated using IBM SiGe technologies, showing their wide-ranging applicability and utility.

Application/Circuit Comments Figure of merit Reference Model-hardware correlation Ring oscillators ECL differential, typically 250–300-mV swing 5HP–16 ps [8], Nortel 7HP – 9 ps, 8HP – 4.2 ps (7HP, 8HP), unpublished Storage PRML read channel Highly integrated BiCMOS design >75 MB/s (600 Mb/s), product [2], IBM RF/WLAN (2–2.5 GHz) Integrated VCO 0.5-µm SiGe, tuning using MOS cap 2.5 V, –95 dBc/Hz at 25 kHz, 9-mA core [9], IBM TDMA power amplifier IS-54-compliant at 800 MHz [10], IBM CDMA power amplifier IS-95-compliant at 1800 or 1900 MHz [10], IBM Wireless LAN chip set Three SiGe chips and one CMOS chip to replace eight GaAs chips Commercial production part in PCM-CIA cards [11], Intersil Wireless down-converter 1-V design, integrated transformer coupling and feedback Mixer 2.5 mA, LNA 2.5 mA at 1 V, LNA 10.5-dB gain, 0.9-dB noise figure [8], Nortel 2.5-GHz frequency synthesizer Three bipolar, four CMOS blocks (200 HBTs, 2500 FETs, ~150 passives) –91 dBc/Hz at 100-kHz offset, 2375–2550 MHz, 1-MHz spacing, 44 mW core [12], IBM GPS chip set SiGe 0.5-µm BiCMOS Direct-conversion front end [13], IBM and SMI Microwave/WLAN (5+ GHz) Integrated VCO Fully integrated L, C, varactor tank To 26 GHz, 3 V, 22-mW core power, 3.6% tune, 84 dBc/Hz at 100-kHz offset [14], IBM Frequency divider 1.9-V, 0.5-µm SiGe BiCMOS 1.9 V, 220 µA, 2.3–5.9 GHz [8], Nortel K-band static frequency divider 1/128, inductively peaked input buffer, 0.5-µm SiGe 23-GHz operation demonstrated [15], HRL Base station Digital, DAC chips 8-GHz clock, highly integrated –140 dBc/Hz dynamic range [16], Siemens Networking Integrated VCO–40G 0.18-µm SiGe, fully integrated To 25 GHz, digital coarse tuning with MOS capacitors [17], IBM Broadband amplifier 0.5-µm SiGe BiCMOS design 9-dB gain, 22-GHz BW, 6-dB NF [18], Nortel Broadband amplifier For optical networking receiver Up to 50 GHz bandwidth in 7HP [17], AMCC High-gain amplifier 0.5-µm SiGe BiCMOS design Integrated 60-dB stable gain for 12.5G [19], Nortel Dynamic frequency dividers Building block, divide by 2 5HP – 50 GHz, 7HP – up to 98 GHz Anonymous, unpublished Multiplexer For SONET applications 5HP – 12.5 Gb/s, 7HP – 56 Gb/s [17, 20], IBM Demultiplexer For SONET applications Up to 45 Gb/s [17, 20], IBM Ser/Des 0.5-µm single-chip solution 12.5 Gbaud [21], IBM Modulator driver Distributed large-signal amplifier Up to 48 Gb/s, 3.5 V peak-to-peak AMCC data sheet Network switch 68 × 69, 150,000 SiGe HBTs 2.5 Gb/s, >200 Gb/s throughput AMCC data sheet 10-Gb/s chip set Complete chip set for STM64/OC-192 designed by Alcatel Mux and demux, laser driver, preamp, limiting amp, CDR (data recovery) [22], Alcatel Data conversion D-to-A converter Analog Devices design 12 bits, >1 GSample/s [23], ADI A-to-D converter IBM Research 4 bits, 8 Gsample/s [24], IBM ∑modulator Fourth-order, 0.5-µm SiGe, LC resonators with Q enhancement 5 V, 350 mW at 4 GHz, max SNR 53 dB, SFDR 69 dB (11 bits) [25], Carleton University Memory Bipolar cache RPI design 0.3 ns access time [26], RPI Ultrawide band Timing generator chip 0.5-µm SiGe HBT design 5 V, 0.5 W, up to 2.5 GHz,2 ps accuracy, 10 ps jitter in a 100-ns window [27], TDSI/SMI Instrumentation Pin electronics driver [28], IBM Digital RISC engine Simulation/analysis of methods to achieve >16-GHz RISC engine SiGe higher HBT count and CMOS integration has major benefits [29], RPI Highly integrated OC48 mapper 0.5-µm SiGe BiCMOS 2.5 Gb/s highly integrated [11], AMCC ASIC test site 1.8M CMOS, ASIC qualification vehicle Equivalent to base 0.5-µm CMOS [30], IBM Radar X-band phase shifters PIN diode circuits with thick metal add-on module (Hughes/Raytheon) 2- and 3-bit fully integrated phase shifters at 6–10 GHz [11], Hughes/IBM

An important aspect of any SiGe BiCMOS technology is the yieldable HBT device count. There are now products with HBT device counts greater than 100,000. A good example is a 68 × 69-cross-point switch¹ which contains more than 100,000 SiGe HBTs. The largest chip to date is a 10.8 × 10.8-mm OC-48c SONET/SDH mapper with integrated serializer/deserializer integrated clock recovery (CDR) and clock synthesis (CSU).² This highly integrated mixed-signal circuit includes 6000 HBTs and 1.2 million CMOS transistors.

The 0.5-µm and 0.25-µm SiGe BiCMOS technologies are ideal for many wireless applications. Areas of analog sections do not scale with decreasing lithography, which reduces the incentive to migrate toward more advanced lithography ground rules [3]. Consequently, a full suite of passive devices is required for any highly integrated mixed-signal chip. The focus in resistors is to achieve good tolerance [~10% on polysilicon (poly) and single-crystal silicon] and reduced parasitic capacitance. For the most stringent requirements, back-end-of-line (BEOL³) thin-film resistors are being added [3]. The thrust for varactors is improved tunability, while maintaining linearity, and high Q (quality factor) values. Capacitors, both front-end-of-line (FEOL) MOS and metallization-based MIM, require higher capacitance per unit area to provide analog area scaling. The performance of spiral inductors continues to be improved by thick metals in spite of skin-effect concerns. Further enhancements include multiple layers of thick metal, deep-trench mazes under the inductor, and polysilicon ground shields.⁴ These features, which are discussed in detail in the section devoted to passive elements, result in passives that are much better than those in conventional silicon CMOS and similar to passives in GaAs ICs.

Although the SiGe HBT transistor is the cornerstone of IBM BiCMOS technologies, many components contribute to their success. Moreover, there are applications which do not require the performance provided by the SiGe bipolar transistor. This application space was addressed by developing rf CMOS technologies as derivatives of the SiGe BiCMOS technologies. The first of these to be qualified, 0.25-µm CMOS 6SFRF, is based on the BiCMOS 6HP and CMOS 6SF technologies. RF CMOS technologies include an extensive suite of passive devices, device models optimized for radio frequency (rf) applications, and a design automation system which is compatible with rf design techniques. For CMOS devices, high-quality passives are critical in achieving a system on a chip (SoC), because of the difficulty of rf matching MOS devices. More advanced rf CMOS technologies are also being developed with minimum linewidths of 0.13 µm and 0.10 µm.

This paper first reviews the active devices (npn HBT and MOS FETs) and passive devices (resistors, capacitors, varactors, and inductors) available in these technologies in detail from a circuit designer's point of view. We present dc and ac figures of merit important for high-performance mixed-signal communications technologies. The tradeoffs involved in device design are also discussed. Included in this section is a discussion on the importance of electrostatic discharge (ESD) technology, with special requirements for rf applications. The next section covers technology development methodology for SiGe BiCMOS and rf CMOS devices. We discuss the qualification methodology and manufacturability of (Bi)CMOS mixed-signal rf technologies. This is followed by a discussion of other technology issues that have implications for circuit and product design. Noise, isolation, and active device reliability are discussed in detail, as well as metal electromigration, which is important for design of a reliable product.

2. Devices for communications technologies

The addition of Ge into the bipolar junction transistor (BJT) by IBM in the late 1980s, creating a heterojunction bipolar transistor, or HBT, enabled higher performance than was believed possible in silicon technologies. A fundamental reason for using a BJT is its exponential change in output current with input voltage. At its peak operating point, the BJT achieves about three times the transconductance, and thus three times the drive capability, of an FET, as illustrated in Figure 3. Retaining the beneficial properties of the BJT, the incorporation of Ge into the base of the device introduced a number of further benefits.

Figure 3

Incorporation of substitutional Ge into the crystal lattice of the silicon creates a compressive strain in the material (because the Ge atom requires a larger atomic separation), and as a result, reduces the bandgap of the material. In a typical HBT (as in GaAs or InP materials), this bandgap difference between layers of semiconductor materials is used to affect the injection of carriers between the two sides of the junctions. Some SiGe HBTs are similar, where the Ge is formed in an abrupt transition to a constant value over a specified width. In the IBM “graded” SiGe HBTs, the Ge content is not a constant, but instead increases (low concentration closer to the wafer surface to high concentration deeper into the device) and thus contains a decreasing bandgap in the direction of electron flow. Figure 4 is a schematic diagram of the Ge concentration and associated band structure illustrating this concept. The electrons are injected from the emitter of the device, having a reduced barrier to injection because of the small Ge content at the junction, and then experience an accelerating field from the increasing Ge content deeper into the device. The electrical effects of this graded Ge content are well documented [31]. The content at the junction increases the electron injection into the base, thus increasing the dc current gain. The Ge grade has the effect of speeding the transport of electrons across the device, resulting in higher-frequency operation. The Ge grade also improves the device Early voltage (flatness of the output current as a function of output voltage characteristics) by modulating the intrinsic carrier concentration across the base. The Gummel characteristic [Figure 5(a)] illustrates the fact that the turn-on voltage for a SiGe HBT compares favorably with III–V HBT devices, and the output characteristic [Figure 5(b)] illustrates very flat characteristics and a sharp “knee,” both favorable to high voltage gain in such a device. The aspect of acceleration of electrons across the device is one of particular importance in scaling the device to higher-speed performance, as is discussed shortly.

Figure 4   Figure 5

Today, IBM is engaged in a number of SiGe HBT device design activities, driven by markets with differing requirements (see the summary of HBT characteristics in Table 2). Even though high-speed performance often gets the attention in SiGe HBT device developments, advances are taking place to address applications that do not demand higher speed but rather higher-voltage operation or lower costs.

Semiconductor chips used in wireless applications such as cellular phones, wireless networks, and global positioning systems (GPSs) are required to be inexpensive. The number of masks and the complexity of processing affect wafer cost and yield, and therefore the final packaged part cost. To achieve cost reductions, wafer processing is simplified by reducing the number of process steps. These reductions can take the form of eliminating a portion of the structure (deep-trench isolation), consolidation of masking steps, or changes to the HBT structure [non-self-aligned (NSA) extrinsic base]. In all situations, the device performance is altered as part of the device customization required for a particular end use.

An example of the cost/performance tradeoff is illustrated by the SiGe 5MR technology, which was tailored for the ±5-V supply voltage used by hard disk drive preamplifiers. These enhancements were also incorporated into SiGe 5HPE. Again, the chip cost was required to be low, and the challenge was to meet both the cost and use voltage criteria simultaneously. While the higher BV_CEO target (9.6 V) was met by increasing the lightly doped collector epitaxial layer thickness, the output characteristics of the high-breakdown HBT suffered from barrier effects [32] caused by base broadening, as shown in Figure 6(a). The usual high values of Early voltage were compromised. Two approaches were taken to improve transistor performance: 1) improve the base Ge profile by introducing the boron within the Ge base layer, and 2) increase the lateral spacing between the extrinsic base implant with respect to the emitter opening, thus decreasing enhanced diffusion of the intrinsic base caused by the extrinsic base implant [33]. These two improvements resulted in a substantially improved V_A, as shown in Figure 6(b). In addition, the peak frequency performance, f_T, was improved from 14 GHz to 19 GHz.

Figure 6

With an increased distance from the extrinsic base implant to the emitter opening, it was more cost-effective to simplify the usual self-aligned extrinsic base structure to a NSA version in which the emitter polysilicon itself was used as the mask for the extrinsic base implant. A 7% reduction in processing time and an equally substantial reduction in wafer cost were achieved. These device improvements were feasible because the circuit designers were willing to trade off higher base resistance for increased frequency performance and Early voltage. Owing to the less complex emitter definition process, the V_BE matching is also markedly improved. These device tradeoffs meet both the circuit design and wafer cost requirements and demonstrate the versatility of the successful IBM SiGe technologies.

In the high-speed arena, SiGe HBTs today are surpassing even the fastest III–V production devices. The key to this achievement is the superior within-device parasitic-control technology available to SiGe device designers, compared to what is available to III–V device designers. With lithographically defined implants, trench isolation, self-aligned low-resistance regions, and options such as spacer technology, silicon device designers have a myriad of tools at their disposal.

The most common measure of performance is f_T, which is the maximum frequency at which the transistor demonstrates useful (i.e., above unity) current gain. The components of f_T are the diffusion capacitance charging relation (kT/qI_E)(C_EB + C_CB), transit times across the device (principally consisting of base transit time _B and collector space-charge transit time _C), and the collector resistance–collector base capacitance R_CC_CB charging time, as shown in Equation (1):

1/(2πfT) = EC (kT/qIE)(CEB + CCB) + RCCCB + B + C.

(1)

Improvements in f_T are achieved by reducing the thickness of each of the layers through which the electrons must travel—the neutral base (i.e., affecting _B) and the collector space-charge region (i.e., affecting _C), as well as reducing the RC charging terms for the parasitic capacitances in the device. This concept is shown in Figure 7(a). The distribution of the boron dopant (which comprises the base) is made narrower; the Ge distribution is also made narrower, and the grade is increased; also, the collector concentration is increased, which reduces the thickness of the space-charge region and at the same time reduces the collector access resistance. We refer to this as vertical scaling of the transistor, since these aspects are not related to the lateral dimensions of the device. The result of vertical scaling is to reduce the transit time and increase the maximum operating current density in the device (i.e., for the same size device, the current to reach maximum f_T performance is increased). Figure 7(b) shows this effect of vertical scaling on a plot of f_T vs. current density.

Figure 7

The second common measure of performance is f_max, which is the maximum frequency at which the transistor has useful (i.e., above unity) power gain; f_max is approximately given by the well-known relationship between f_T and parasitics,

fmax (fT/8πRBBCCB)1/2,

(2)

where R_BB and C_CB are respectively the parasitic base resistance and collector–base capacitance. For most applications, it is required that the f_max value be at least comparable to the f_T value for optimal circuit performance. Achieving high f_max is a challenge from the point of view of both device design and process, since it is a strong function of the device structure, which largely determines the values of R_BB and C_CB. This is because the majority of R_BB and C_CB are present in the extrinsic part of the device, or that region of the device which is not an essential part of the carrier transport. This fact provides the expectation that f_max will continue to be substantially improved with new device structures.

Comparison of the IBM SiGe HBT device structures illustrates how improvements in device structure may provide increases in the figure of merit, f_max. Through several generations of technology, IBM has utilized the same device structure, often referred to as the epitaxial transistor (ETX). Its identifiable structural characteristic is an extrinsic base implanted into the SiGe epitaxial film. Through careful analysis, depending heavily on 2D simulations [34], it was determined that this structure has some significant limitations. Implants into the silicon create lattice defects, which affect the diffusion of the intrinsic base boron, increasing _B and thus reducing device performance. This limits how close the implant may be placed to the intrinsic device, and therefore creates a lower limit on the achievable base resistance, R_BB. The implanted extrinsic base also extends deep into the silicon and intersects the collector implants at a high concentration, which results in high C_CB. Shown in Figure 8 are the ETX structure and the structure IBM is pursuing with a raised extrinsic base (RXB) to substantially reduce R_BB and C_CB. The raised extrinsic base has less influence on the intrinsic dopant diffusion and may be placed in close proximity to the intrinsic device, thus reducing R_BB without impact to f_T. It also has a minimal junction depth, and, as such, has a relatively small C_CB.

Figure 8

Initial results on the RXB structure demonstrate its benefits over the ETX structure. While retaining the f_T performance of a structure without a self-aligned extrinsic base (indicating no influence of the extrinsic base on the intrinsic base), the base resistance has been reduced by a factor of approximately 2, and C_CB has been maintained constant compared to a previous-generation device of similar area, with lower f_T. This results in simultaneous f_T and f_max improvements between generations of more than 80% (Figure 9).

Figure 9

The CMOS device takes on different roles whether offered as part of a BiCMOS technology, where the bipolar device is available for analog functions, or as part of a CMOS-only technology, where the FET devices must take a primary role in analog functionality. From device design, device layout, process development, characterization, and modeling, this differentiation influences technology development. This section discusses not only the digital design aspects of FET devices, but also aspects that are driven by analog requirements, such as the ability of these devices to withstand higher voltages or have lower back-bias sensitivity (body effect) or higher self-gain (g_m/g₀). These aspects were less important in BiCMOS processes because of the presence of the bipolar device, but in CMOS-only technologies they become more essential. Thus, one finds as a requirement that additional masks and complexity be present in CMOS processes, and a greater variety of FET devices are offered to designers.

When offered as part of IBM SiGe BiCMOS technologies, the CMOS devices are used primarily for integrating digital logic functions with high-speed bipolar analog circuits. This allows fully integrated system-on-a-chip products, with the CMOS performing the lower-frequency baseband signal processing. The logic functionality is streamlined by offering ASIC library elements from the base CMOS technology to be integrated with the rf analog circuits. The CMOS devices can also be used for low-frequency analog functions such as A-D converters, multiplexers, and switches. CMOS devices have one large advantage over bipolar devices: There is essentially no gate current. This makes CMOS devices ideal in circuits where it is required to measure the charge on capacitors such as A-D converters. Bipolar devices would drain the charge during the measurement.

Development of CMOS devices for digital logic purposes is driven primarily by shrinking the device dimensions, thinning the gate oxide, and lowering supply voltages to achieve faster performance, increased density, and lower power consumption. The smaller device lengths lower the parasitics and increase f_T, but also necessitate complex designs including halo implants to minimize short-channel effects and control punch-through. These implants have negative effects on important analog characteristics such as self-gain (g_m/g₀). Also, the thinner gate oxides in the advanced logic devices cannot support the higher voltages required in analog circuits. Additionally, gate current becomes non-negligible. The solution to this is a dual-oxide technology. The analog devices are designed with thicker oxides, longer channel lengths, and unique source/drain extensions. This added process complexity allows placement of high-performance logic devices and high-voltage analog devices on the same chip.

Some specific parameters such as noise and V_t matching must be considered when designing analog CMOS devices. Noise is not a large concern in digital CMOS circuits, and some processes such as nitrided gate oxide actually increase noise in a tradeoff for decreased dopant penetration of the gate oxide and improved hot-carrier degradation. V_t matching in analog circuits is much more critical than in logic circuits, and all variables that introduce mismatch, including process and layout, must be minimized.

IBM has four SiGe BiCMOS technologies and one CMOS rf technology qualified for high-volume production: SiGe 5HP, SiGe 5HPE, SiGe 6HP, SiGe 7HP, and CMOS 6SFRF. SiGe 5HP and SiGe 5HPE are single-gate-oxide technologies, while the rest have an optional dual-gate-oxide process. SiGe 5HP contains 3.3-V CMOS devices designed specifically for logic support in the BiCMOS technology. SiGe 5HPE has a 12-nm gate oxide, 5-V CMOS with an additional isolated n-FET device. The iso-n-FET is a standard n-FET surrounded by an isolation tub which allows the iso-n-FET p-well to be biased independently from the substrate. Independent well biasing enables a circuit designer to handle dual logic levels on-chip, for example by biasing the substrate at –5 V and the p-well in the tub at 0 V. Higher-voltage analog signals can also be handled in this way by stacking 5-V FETs inside and outside the isolation, with a 10-V signal across the combination. Iso-n-FET devices also have better noise isolation owing to the independently biased p-well and isolation tub.

The dual-oxide technologies are SiGe 6HP, CMOS 6SFRF, and SiGe 7HP. SiGe 6HP contains 2.5-V and 3.3-V CMOS devices, which have 5-nm and 7-nm gate oxides, respectively. The thin-oxide FETs, with 0.25-µm L_min (minimum drawn gate lengths), are used for the high-speed logic, while the thick-oxide devices are 0.4-µm-L_min n-FETs and 0.34-µm-L_min p-FETs. The thick-oxide FETs enable 3.3-V I/O compatibility as well as analog signal handling. CMOS 6SFRF is based on the same 2.5-V/3.3-V devices, with an additional 2.5-V iso-n-FET and a process option of 6.5-V thick-oxide (14-nm) devices in place of the 3.3-V devices. The 6.5-V devices have L_min = 0.7 µm to support the higher voltage. These devices can be used as low-frequency power amplifiers (amps), high-voltage analog switches, and voltage regulators in battery chargers. SiGe 7HP has 1.8-V and 3.3-V CMOS devices with 3.5-nm and 6.8-nm gate oxides, respectively. There are 1.8-V standard-V_t FETs and optional 1.8-V high-V_t FETs, 3.3-V FETs, and both 1.8-V and 3.3-V iso-n-FETs. The 1.8-V FETs have L_min = 0.18 µm and the 3.3-V FETs have L_min = 0.4 µm. Table 3 compares some of the key parameters of each technology.

The main purpose of the CMOS devices in a BiCMOS technology is to provide integrated logic functionality. The logic design can be expedited by using ASIC library “books” already developed for the base CMOS technology. This approach can be used only if the CMOS device characteristics in the BiCMOS technology closely match those of the base CMOS technology. Many process differences can lead to significant device differences. Adjusting the process minimizes many of these differences, but some cannot be corrected. To verify that the ASIC library elements function correctly and that the CMOS timing models are still valid for the BiCMOS process, ASIC library test sites are built in the BiCMOS process. The chips are tested for functionality, and hardware-to-model correlation is done to validate the timing models. Because some devices are known not to function correctly owing to process differences, any library elements containing these devices are not tested. In Figure 10, a typical correlation plot with both SiGe and CMOS data shows that the same model can accurately represent both technologies.

Figure 10

BiCMOS technology development in IBM has been focused largely on the integration of high-performance SiGe HBTs in a base CMOS technology. In general, passive devices are developed from existing processes used for these transistors; i.e., resistors are formed from CMOS FET source/drain implants, MOS capacitors from the reach-through implants used for the HBT collector contact and FET gate oxide/polysilicon gate, and inductors designed using last-metal options for these technologies. The need for high integration and technology innovation in rf circuit design has changed the direction of passive development in the last several years. Passive devices which in some cases utilize processes not used for transistor manufacture have allowed the development of high-performance devices enabling rf technology innovations. Examples are thick analog metals (AMs), e.g., 4-µm Al, used as last-metal options for high-Q inductors; TaN resistors integrated in the back-end-of-line (BEOL) metallization for low parasitic capacitance/tolerance; and high-capacitance nitride metal-insulator-metal (MIM) capacitors.

Balancing the performance of passive devices with processing costs is a challenge. Some of the more critical parameters for the passive elements used in rf designs are resistor tolerance, varactor tunability (C_max/C_min) and linearity, MIM capacitance density and quality factor (Q), and inductor Q. In the following sections, the important passive elements offered in the IBM SiGe BiCMOS and rf CMOS technologies are described, with focus on their rf application, key figures of merit, and reliability.

Resistors

Resistors are used in all analog and mixed-signal circuit blocks. A wide variety of resistors are offered in the IBM SiGe BiCMOS and rf CMOS technologies to accommodate designer needs (see Table 4). Figures of merit for resistors are sheet resistance, tolerance, parasitic capacitance, voltage, and temperature coefficients. Three types of basic resistors are used in the SiGe BiCMOS process to achieve the desired properties and resistance ranges needed in analog circuit designs: p-doped polysilicon resistors, n- and p-type diffusion resistors, and BEOL TaN metal resistors.

Table 4   Electrical parameters of resistors available in SiGe and rf CMOS technologies.

Resistor Sheet resistance (/;) Tolerance (%) TCR (ppm/°C) Parasitic capacitance (fF/µm2) Maximum current (mA/µm) p+ polysilicon 270 10–15 21 0.11 0.6 p polysilicon 1600 25 –1105 0.09 0.1 n+ diffusion 72 10 1751 1.00 1.0 n subcollector 8 15 1460 0.12 1.0 TaN metal 142 10 –728 0.03 0.5

Highly doped p-type polysilicon resistors are preferred in most cases for mixed-signal and analog applications because of their good matching, low parasitic capacitance to the substrate, and excellent temperature coefficient, as shown in Table 4. These resistors consist of gate or SiGe polysilicon doped with a high-dose boron implant, normally the p-FET source/drain implant. Either shallow-trench isolation or shallow/deep-trench isolation is used under these resistors to reduce parasitic capacitance between the resistor and substrate. The ends of the resistor are silicided for low contact resistance to the BEOL wiring, and the body of the resistor is covered with silicon nitride to block the silicide. The p+ polysilicon resistor has a sheet resistance of 270 / and a 10–15% tolerance. Low tolerance is essential for efficient compact circuit designs. Table 4 shows that this resistor has a very low temperature coefficient (TCR) of 21 ppm/°C, which is 2–3% the TCR of the other resistors offered. This makes the resistor most attractive for circuit applications owing to low variation in resistance with changes in temperature over typical ranges of –40°C to 125°C. The parasitic capacitance between the resistor and substrate is 10% of that of a diffusion resistor but four times the value for a BEOL resistor because of the distance of these devices from the substrate. A low-doped p-type polysilicon resistor is offered in these technologies as well. This provides a higher sheet resistance at 1600 / for applications requiring high resistance while maintaining good parasitic capacitance. This resistor is more difficult to control in the process, resulting in a 25% tolerance.

The n+ diffusion resistor is formed with the n-FET source/drain implant in single-crystal silicon. The ends of the resistor are silicided. With a sheet resistance of 72 /, the n+ diffusion resistor is used in current source/biasing circuits where resistors in the range of 50–100 are needed. Since this resistor is made from the FET source/drain, it has a high capacitance which limits its use. This resistor is typically controlled to a 10% tolerance.

An NS resistor is made from the low-resistance npn subcollector and contacted with the collector contact. This device has a low sheet resistance at 8 / and a tolerance of 10–15%. Typical of diffusion resistors, this device has a high temperature coefficient at 1460 ppm/°C. This resistor is ideally used as a ballast resistor in applications such as power amplifiers.

A thin-film BEOL resistor has several attractive features, such as low tolerance, low parasitics, and the ability to make design changes with short lead times. A TaN resistor is offered in several of the IBM SiGe BiCMOS technologies at metal levels M1 and M5. This device consists of a TaN film contacted by metal vias. The tolerance is low at 10%, and because of its distance from the substrate, it has very low parasitic capacitance to the substrate.

All resistors offered in the IBM SiGe BiCMOS and rf CMOS technologies meet stringent reliability requirements for 100,000 power-on hours. Reliability tests are performed by measuring the shift in resistance over a fixed period of time under constant current. By varying the bias conditions used to stress these devices, the amount the resistor will shift in 100,000 hours can be projected. Typically, resistance changes of less than several tenths of a percent are projected over the life of the resistor for the current limits specified in Table 4. Current limits of 1 mA/µm of width for diffusion resistors are normal. Low-resistance polysilicon and BEOL resistors have a current limit of 0.5–0.6 mA/µm.

Capacitors

Passive devices, such as inductors, resistors, and capacitors, dominate the component count in modern wireless appliances. A passives-to-active device ratio of 20:1 is commonplace on a typical off-the-shelf cellular phone [35]. To reduce form factors of handheld devices, traditional surface-mounted passives are being integrated into the chip. Three types of capacitors have been developed in SiGe technologies to meet customer requirements for reduced board-level components. MOS (polysilicon gated capacitors on single-crystal silicon), PIP (polysilicon-insulator-polysilicon), and MIM (metal-insulator-metal) capacitors each have their own place for use in different application spaces depending on capacitance desired and performance at the application frequency. An overview of process details for optimization, electrical performance, and reliability will be given for each device.

The simplest MOS capacitors are formed without additional masks from the FET elements in all SiGe BiCMOS generations using silicided gate polysilicon, thin gate oxide, and FET well-doped silicon. Although these devices have a very high capacitance per unit area owing to the ultrathin oxide, they are not particularly useful for rf applications because of the high resistance of the well doping (~250 /) and poor voltage coefficient. A more optimized capacitor has been developed by heavily doping the silicon substrate to reduce parasitic resistance [2]. This is accomplished by using a high-dose phosphorus reachthrough implant (~25 /) to dope the bottom plate of the capacitor. During gate oxidation, the insulator grown over high-dose phosphorus implants can result in a 50–100% increase in thickness relative to oxides grown over intrinsic silicon because of enhanced oxidation. Shallow reachthrough implants can cause unreliable oxides due to very high growth rates driven by high surface-dopant concentrations. The quality of oxide grown over the diffusion region increases significantly with implant depth. A comparison of the applied field in depletion mode at a 1-nA leakage current showed that a shallow implant causes premature oxide leakage (at 5.2 MV/cm) relative to the deeper implant (6 to 7 MV/cm), which meets leakage requirements. Therefore, an optimized MOS capacitor will have a high-dose reachthrough implant at a moderate depth for low resistance and a reliable oxide.

PIP capacitors are fabricated in double-polysilicon BiCMOS processes [36]. The unit capacitance is a product of the integration methodology, and typically the device does not require an additional process step. Fabricated only in SiGe 5HPE, the capacitor structure is formed using p+-doped gate polysilicon as the bottom plate, a deposited oxide layer for the capacitor dielectric, and silicided extrinsic base polysilicon as the top electrode. To minimize the bottom-plate capacitance to substrate, the doped gate polysilicon is patterned over shallow-trench isolation and/or deep-trench maze, an advantage gained over the MOS structure. The dielectric quality is critical to ensure high reliability and robust breakdown strength. Thermal oxides are rarely used, because the polysilicon roughens along grain boundaries during oxidation, yielding high field points that reduce the breakdown strength. An obvious alternative is PECVD dielectric, but these dielectrics typically have poor uniformity, poor conformality, and pinholes in thin films. For this application, a thin deposited hot thermal oxide (HTO) was developed. The HTO breaks down in the range of 9–10 MV/cm and is very conformal, yielding full thickness coverage at the gate polysilicon corners where premature breakdown can occur under high electric fields. Optimizing linearity for the PIP capacitor was an important aspect of its development. To understand C–V linearity as a function of dopant type and dose, experiments were designed which varied dopant type and concentration for each of the capacitor electrodes. The total capacitance and linearity are a function of the polysilicon depletion capacitance in series with the dielectric capacitance. In the optimal electrode configuration, both plates of the device are doped n-type. At a given bias, one plate is in depletion while the other plate is in accumulation, causing a small change in the net capacitance. In contrast, when one plate is doped n-type and the other p-type, the plates are simultaneously in either depletion or accumulation, causing a larger change in the net capacitance, which results in reduced linearity.

While acceptable for use in low-frequency applications, MOS and PIP capacitors suffer from low quality factors (Qs) due to high-resistance plates and capacitive losses in the 2–10-GHz range, rendering them nonideal or limiting their use. A novel metal-insulator-metal capacitor (MIMCAP) was developed which takes advantage of low-resistivity metal wiring and of a thick interlevel dielectric which physically distances the devices from the relatively low-resistivity substrate and the planar back-end-of-line (BEOL) topology in order to build in high reliability [37]. The SiGe BiCMOS planar MIM (Figure 11) is fabricated by depositing a 50-nm PECVD oxide and a 200-nm metal stack on top of any metal wiring level except the first and last. A mask is applied and the top plate is etched, stopping at the capacitor dielectric. The metal layer mask, which defines the metal wiring as well as the base capacitor plate, is then applied. An interlevel dielectric is deposited and planarized, and vias added to connect to the next metal layer. The dielectric of the MIM capacitor is thicker than those of either PIP or MOS capacitors because lower-temperature dielectrics (compatible with BEOL processing) are generally of poorer quality than higher-temperature CVD or thermal oxides.

Figure 11

Designers prefer the MIM capacitor over the other two types because of its advantageous performance (higher Q) at higher frequencies. Thick metal plates offer lower resistance than doped and/or silicided polysilicon, and placement in the interconnect levels significantly reduces the parasitic capacitance of the substrate. Finally, the ability to resize the MIM in a BEOL redesign reduces cycles of learning, a benefit not available with silicon-based capacitors. The penalty paid for these benefits is that a large area of the chip is consumed, affecting the ability to reduce the form factor of the chip. Capacitors may require as much as 50% of the chip area, depending on the application. In order to decrease the capacitor footprint, several options to increase the unit capacitance are available, since capacitance is a direct function of the dielectric constant of the insulator and is inversely proportional to film thickness.

The list of requirements which a high-dielectric-constant material must meet in order to address manufacturing, yield, design, and reliability concerns is a long and demanding one. Table 5 contains a short list of critical parameters. From a fabrication aspect, the deposition process must meet manufacturability targets, have slow and controllable deposition rates, have high throughput, and have no impact on BEOL yield or parametrics. From a design aspect, the new dielectric should not significantly change ac device models established from prior generations. Finally, the film must have low defect density and negligible fixed or mobile charges, and it must be stable under thermal stress in order to pass stringent reliability qualification.

Table 5   Critical parameters for high-k dielectrics required for MIM capacitors.

Property Value Deposition temperature <400°C Thickness uniformity <5% (3) Deposition rate 30–50 nm/min TCC <30 ppm VCC <100 ppm Operating voltage ±5 V Reliability <10 ppm at 100K POH Leakage 10-6 A/cm2 at ±5 V Dielectric constant 7 to 25 TCC = temperature coefficient of capacitance; VCC = voltage coefficient of capacitance.

A processing limitation for all new dielectrics will be deposition temperatures of ~400°C or less to prevent the shorting of narrowly spaced large metal lines due to metal extrusions. PECVD nitrides are known for their relatively high hydrogen content, bonded to both silicon and nitrogen. Recently, a PECVD nitride has been qualified which increases the capacitance per unit area by 43% over prior oxide dielectric. Aluminum and tantalum oxide processes are coming on line, driven primarily by next-generation CMOS gate-oxide replacement and DRAM node capacitors. These deposition processes cover the spectrum from atomic layer to bulk CVD, and often require clustering with rapid thermal process modules to fully oxidize the unreacted carbon compounds derived from the source material. Very-high-k and ferroelectric films such as composites of barium, strontium, bismuth, and titanium are still two to three generations away from implementation [38].

Finally, by taking advantage of the planarity and modularity of integration, wiring MIM capacitors in parallel on two or more levels can yield an equivalent multiple increase in unit capacitance, albeit at the cost of a mask level for each. Similarly, in SiGe 5HPE, the MOSCAP and PIP capacitors can be integrated into one structure and wired in parallel to yield a total unit capacitance of 2.8 fF/µm².

The planar MIMCAP concept and fabrication techniques have been successfully transferred to all SiGe generations as well as CMOS 5/6 technologies. The fabrication strategy has also been used to integrate the device into copper BEOL (CMOS 7/8) [39]. The integration of more advanced CMOS technologies into a copper BEOL presented many challenges that ultimately resulted in a process similar to that of the aluminum MIMCAP. Approaches using the copper level as the bottom plate in a fashion analogous to the aluminum approach were not successful because of issues associated with copper metallurgy (formation of hillocks or extrusions), the requirement of large copper areas for oxide plugs for chemical-mechanical polishing (CMP) in order to achieve planarity, and because copper was oxidized during the deposition of a dielectric which required oxygen, thereby precluding the direct deposition of all oxides. The so-called MOD (MIM over dielectric) provides a planar starting surface, relief from copper exposure to oxidizing and chlorine etch ambient, and capacitor size constraints. Plate materials and thickness are designed to be able to fit within the dual damascene stack while not affecting wiring and via parametrics and yield.

Table 6 summarizes key parameters for the optimized capacitor structures, comparing capacitance per unit area temperature linearity (T_CC) and voltage linearity (V_CC). The polysilicon-insulator-polysilicon (poly-poly, or PIP) capacitor has improved parasitics relative to the MOS capacitor because it is over shallow-trench isolation (STI). Area capacitances of the bottom plate to substrate are 1/10 the parasitics for the bottom plate of the MOS capacitor. The PIP capacitor can have a reduction in bottom-plate-to-substrate parasitics for a device over STI/deep trench (DT) relative to a device over STI only. Because the MIM capacitor is produced in the BEOL, it has the lowest parasitics of the devices described. The area capacitance of the bottom plate to substrate is significantly lower than that for the PIP capacitor over DT when the MIM is at M5. However, the MIM perimeter parasitics are much higher. In the 2–4-GHz frequency range, the MIM has the highest Q of the devices described. For a 20-µm × 20-µm device, the MIM has a Q of 90 and the MOS capacitor a Q of 20. A comparison of the MOS and PIP capacitors for a 10-µm × 50-µm device shows Q values of 3 and 6, respectively.

Reliability is central in the design and development of capacitors for BiCMOS technologies. The goal is to maximize capacitance by reducing dielectric thickness while still maintaining acceptable reliability at the rated use voltage. Capacitor reliability is determined using a time-dependent dielectric breakdown (TDDB) test. The devices are biased at high electric fields to accelerate the time to failure. The failures are plotted as a Weibull distribution plot at multiple stress voltages, and then converted to a lifetime plot (Figure 12) to extrapolate to 100,000 power-on hours to determine the electric field the capacitor will survive for this period of time. The MIM capacitor is less reliable than the MOS or PIP capacitors. This result is expected, since the MIM oxide is a PECVD oxide, while the MOS and PIP capacitors are higher-quality oxides. Therefore, the MIM must have a thicker oxide and lower capacitance to meet the same reliability requirements. Also, the PIP capacitor shows reliability results equivalent to those of the MOS capacitor, indicating that a high-quality CVD oxide can be as robust as a thermally grown oxide over n+-type diffusion.

Figure 12

Capacitors are used in a variety of low- and high-frequency applications ranging from power-supply bypass and decoupling to resonators, filters, and tank circuits. MIM capacitors with Q values of 90 at 2 GHz are preferred in narrow-band applications such as resonators, filters, and tank circuits, in which high Qs and low parasitic capacitance are required [40]. In contrast, PIP and MOS are typically used for power-supply bypass and decoupling. With an optimized PIP capacitor using an n+/n+ polysilicon stack, the device could have Qs approaching 30 and would be appropriate for low-frequency rf applications.

The device parameters, process, and reliability issues have been reviewed for the MOS, PIP, and MIM capacitors. The MIM has the lowest series resistance and parasitics, resulting in the highest Q of the three devices by taking advantage of low-resistivity metal plates and presence in the interconnect levels. However, a tradeoff is made, since it has a lower capacitance to compensate for its lower reliability. The MOS capacitor is on the other side of the spectrum, with high capacitance and reliability but with poor linearity and parasitics. The PIP capacitor is a higher-capacitance device; when designed over deep-trench isolation, it offers low parasitic capacitance as well. By selecting the proper dopant polarities, the linearity of the PIP can approach that of the MIM. The device has better linearity than the MOS capacitor, and if both polysilicon plates are similarly doped, very good voltage coefficients can be achieved.

Varactors

Varactors are essential elements of some key rf circuits, such as voltage-controlled oscillators (VCOs), phase shifters, and frequency multipliers. The key figures of merit for varactors are 1) tunability (C_max/C_min); 2) CV linearity for VCO gain variation; 3) quality factor Q; 4) tolerance; and 5) capacitance density. Traditionally, the varactor offered in BiCMOS technologies is the standard collector–base (CB) junction varactor. Three varactors have been developed for the SiGe BiCMOS and rf CMOS processes to augment this offering. These are a “quasi-hyperabrupt” enhancement of the CB diode, a MOS accumulation mode capacitor, and a CMOS diode.

Because it relies on the doping profile of the existing SiGe heterojunction bipolar transistor (HBT), the standard CB diode is not optimum for rf circuit performance. This is evidenced by a tunability of 1.7:1 between 0 and 3 V and a low degree of linearity, as shown in Figure 13. To overcome these problems, the quasi-hyperabrupt (HA) varactor utilizing a retrograde implant to modify the CB doping profile has been developed. To ensure independent optimization of the varactor and the HBT, an extra mask is used to introduce the retrograde implant. The quasi-hyperabrupt device has excellent VCO circuit performance owing to an outstanding tunability of 3.4 (0, 3 V) and a high degree of linearity, specifically in the 0-to-2-V range (see Figure 13). The extra mask is compatible with an interdigitated layout, thereby preserving the high Q of the device. Figure 14, which is a plot of Q as a function of frequency measured at various biases, demonstrates that the device has a Q in excess of 100 at 2 GHz.

Figure 13   Figure 14

The MOS varactor is an n-channel MOSFET fabricated in an n-well. The capacitance of this varactor is high in accumulation and decreases sharply as the device enters and goes further into depletion. This results in excellent tunability, as shown in Figure 13. The tunability is further enhanced with technology scaling, since the gate-oxide capacitance increases as the gate oxide becomes thinner. However, the MOS varactor can have lower Q because of the series resistances associated with the n-well. To maximize Q, our MOS varactor features an interdigitated layout. Interdigitating the source/drain regions minimizes the n-well series resistance, resulting in a high quality factor. The MOS varactor can be built in rf CMOS as well as BiCMOS technologies without using any extra masks.

The CMOS diode utilizes the halo typically present in state-of-the-art p-FETs to achieve the desired hyperabrupt doping profile. The varactor is basically a p+/n-well diode. The tunability is optimized by maximizing the gate-bounded perimeter and thus the overall area of the halo. The CMOS diode exhibits a tunability of about 1.7:1 over a 3-V range. This varactor can be useful for rf CMOS technologies that require better varactor linearity than a MOS varactor.

Inductors, transmission lines, and transformers

The need for high-performance passive elements in SiGe BiCMOS and rf CMOS technologies has become increasingly important recently because of the technology and integration requirements of high-functionality/low-cost rf circuit applications. On-chip passive elements, specifically monolithic spiral and multilevel spiral inductors, are a key component of these passive offerings. On-chip integration of spiral inductors poses numerous challenges. Issues related to Q, parasitics, manufacturability, design, and cost must be balanced in order to provide a competitive inductor offering [42]. For high-performance inductors, it is necessary to provide thick metallization with low via resistance for reduced series resistance [43]. The typical interconnect scaling associated with digital circuit technologies (thinning metal and dielectric levels to increase wiring density) is inconsistent with the need to keep series resistive losses low for high-quality inductors. Additionally, minimizing substrate losses due to eddy currents and capacitive coupling is desirable in order to increase Q. Integrating the inductors in the last, thick metal levels of the BEOL and using large vias to provide a thick dielectric between the inductor and substrate helps reduce these effects [44].

Three basic metallization options are provided for spiral inductors in the IBM SiGe BiCMOS and rf CMOS technologies: a 2-µm-thick aluminum level, a 4-µm-thick aluminum level, and a dual-metal stack of 4 µm aluminum and 3 µm copper. Figure 15 shows the integration of these levels in the BEOL. These inductor offerings have evolved over the last five years to provide high-performance inductors as rf circuit function and integration needs have evolved. Initially, the SiGe 5HP BiCMOS technology was qualified in 1998 with 2 µm Al as the last metal [45]. As can be seen from Table 7, this aluminum layer has a relatively high sheet resistance (14 m/); therefore, a peak Q for a 1-nH inductor at 2–4 GHz is in the range of 5 to 9. The need for higher-Q inductors drove the qualification of SiGe 5AM, an upgrade to the 5HP process with a 4-µm Al layer for improved inductor performance [2]. This layout has a 4-µm-high via below it to allow for an additional thick interlayer dielectric (ILD) between the inductor and substrate. For a 1-nH inductor, a peak Q of 18 can be realized with the 4-µm Al inductors in SiGe 5AM at a frequency of about 5 GHz. The underpass, an 0.8-µm-thick aluminum layer, has a high sheet resistance relative to the thick aluminum layer. This fixed underpass resistance shows up in series with the relatively low resistance of the 4-µm aluminum spiral metallization, limiting the achievable peak Q.

Figure 15

Table 7   Metal options available for fabricating high-quality passives such as inductors or transmission lines.

Metal Sheet resistance (m/) Peak Q– 1 nH/2–4 GHz 2 µm Al 14 5–9 4 µm Al 7 18 4 µm Al/3 µm Cu 3.2 28

The latest IBM SiGe offering includes an additional two thick, low-resistivity metal levels above the standard BEOL stack (“dual metal”). This stack was qualified for production in November 2001. The uppermost level is thick aluminum compatible with wire bonding or C4 interconnections, with a second thick level composed of copper. Each of these levels has an additional 4 µm of oxide below it to increase the dielectric spacing from level to level and between the two levels and the substrate (see Figure 15). This high-performance offering allows not only high-Q inductors (achieved by paralleling the two thick metals for extremely low series resistance), but also high inductance density (achieved by connecting a spiral from the thick aluminum level in series with a spiral stacked below it on the thick copper level). The dual-metal inductor shown in Figure 16 has a peak Q of 28 over a very large frequency range. Efficiently coupled structures such as transformers (impedance matching and power splitting) and baluns (balanced–unbalanced transformers used to convert differential signals to/from single-ended signals and achieved by vertically stacking windings) are also possible, with a 1:1 balun achieving a 3.5-dB untuned insertion loss. In addition to the two thick levels, an optional polysilicon shield is offered that can increase the peak Q by as much as 30% for certain geometry spirals in addition to reducing substrate noise coupling from the spiral.

Figure 16

The high-quality inductors achievable with the IBM dual-metal technology enable designers to integrate high-Q resonant circuits in support of low-phase-noise VCOs, narrow-band filters, low-loss-impedance matching, etc. The added ability to achieve high-quality integrated magnetically coupled structures permits the realization of on-chip baluns and transformers. Another unique advantage of using two thick metal levels with a large separation distance is the ability to create nearly ideal microstrip and/or coplanar waveguide (CPW) transmission lines with very low loss. Typical CMOS/BiCMOS/SiGe technologies are not able to achieve low-loss, ideal transmission lines because of the excessive series losses and high capacitive coupling inherent in CMOS metallization schemes.

ESD protection devices

Electrostatic discharge (ESD) protection of rf products becomes important as application frequencies exceed 1 GHz. At application frequencies below 1 GHz, the ability to simultaneously achieve excellent ESD protection and performance objectives was possible in most CMOS, BiCMOS, and SOI applications. As semiconductor applications extend beyond 1 GHz, providing ESD protection while simultaneously satisfying performance goals, such as low capacitance on I/O pads, will increase in difficulty.

RF CMOS can utilize some of the traditional ESD solutions that are common in the industry, although many ESD solutions are unacceptable because they preclude low capacitance, high Q, and low noise. MOSFETs have significant 1/f noise and capacitance loading, making diode-based and diode-configured ESD implementations the preferred solutions for rf applications [46]. The integration of shallow-trench isolation (STI) has allowed for both optimization and scaling of the STI-bound p+/n-well diode, the STI-bound n+/substrate diode, and n-well-to-substrate diode structures from 0.5-µm to 0.1-µm CMOS technologies [46–49]. To maintain a constant ESD robustness in order to counter the impact of dimensional scaling from MOSFET constant electric field scaling theory, constant ESD scaling theory indicates that ESD robustness can be preserved by increasing the n-well retrograde dose with successive technology generations [46]. With the introduction of the high retrograde well dose, the p+/n-well diode capacitance can be maintained by adjustment of the n-well implant energy [46–49]. For rf technologies, the introduction of low-doped p-substrates allows for lower n+/substrate and n-well-to-substrate diode capacitance, as well as noise isolation of the ESD elements on adjacent circuitry [50–53]. RC-discriminator networks, whose RC time constant is tuned to the ESD pulse rise time, are also utilized for triggering large MOSFETs located between power supplies.

RF BiCMOS SiGe technologies offer even more opportunity to introduce low-capacitance, high-Q, low-resistance robust ESD elements for ESD protection of rf circuitry. First, for mixed-signal chips that contain digital, analog, and rf circuitry, different ESD solutions can be applied to different functional circuit blocks. The aforementioned CMOS ESD diode elements and RC-triggered MOSFET ESD power clamps can be utilized for the digital functional block. Additionally, with the myriad of additional elements offered by BiCMOS technology, new ESD elements and circuits can be utilized to provide ESD protection of digital, analog, or rf networks. This is possible by taking advantage of the SiGe library elements and the SiGe npn base, subcollector, and isolation structures. SiGe passive elements such as SiGe varactors and SiGe Schottky diodes, as well as active SiGe HBT npn devices and SiGe HBT pnp transistors, can be utilized in either diodic or bipolar configurations for networks [54–58]. Low-capacitance emitter–base and base–collector junctions provide well-controlled high-Q junctions for ESD protection networks. Low diode anode series resistance is achievable in SiGe heterojunction bipolar transistor devices because of the high base doping concentration utilized in heterojunction transistors. Heterojunctions decouple the emitter–base junction capacitance from the base doping concentration design point. For ESD structures, this allows for improved current uniformity in multi-finger base–collector diode structures. Additionally, low diode series cathode resistance, significantly lower than the CMOS well design point, is achieved using the heavily doped subcollector, reach-through, and collector implants. Additionally, removal of the Kirk-effect limiting pedestal implant lowers base–collector junction capacitance for usage of SiGe varactors in the forward-bias mode with no ESD robustness degradation. Deep-trench isolation also provides for the use of deep-trench (DT)-bound subcollector–substrate, DT-bound n-well-to-substrate, and DT-bound p+/n-well diode elements. The DT-bound structures can provide low capacitance, improved latchup immunity, and noise injection reduction, as well as higher density.

BiCMOS SiGe technology also allows for the introduction of scalable ESD power clamps for analog and rf functional blocks. To provide an ESD solution that naturally scales with the BiCMOS technology and utilizes the limitation of bipolar transistors, ESD power clamps were designed which take advantage of the Johnson limit of SiGe HBT devices [59–61]. The Johnson limit can be simply explained as the product of the breakdown voltage and cutoff frequency of a transistor being a constant, V*_mf_T = const. Thus, f_T can be traded off against breakdown voltage.

Hence, from the Johnson limit, V*_mf*_T is associated with a first transistor, and V_mf_T is associated with a second transistor. The ratio of breakdown voltages can be determined as (V*_m/V_m) = (f_T/f*_T). Using this Johnson relationship, an ESD power clamp can be synthesized in which a trigger device with the lowest breakdown voltage can be created by using the transistor with the highest cutoff frequency (f_T), and a clamp device with the highest breakdown device will have the lowest cutoff frequency. Figure 17(a) shows an example of a Darlington-configured bipolar power clamp with a 47-GHz/4-V BV_CEO trigger device that supplies the 27-GHz/6-V BV_CEO clamp device. A 7- ballast resistor was used for each leg of the clamp device. A 7-k bias resistor was used below the trigger device to limit the current. In this power clamp, the trigger device had an open base configuration, allowing early breakdown of the trigger circuit. Figure 17(b) shows the human body model (HBM) ESD results. In a given BiCMOS SiGe technology, a large number of SiGe HBTs with different breakdown voltages are available to establish different trigger conditions for applications with different power supplies.

Figure 17

There are many advantages of the BiCMOS SiGe ESD clamp compared to RC-triggered MOSFET ESD power clamps. First, SiGe ESD power clamps provide a much higher robustness per unit micron. The RC-triggered MOSFET ESD power clamp achieves less than 2.5 V/µm, while the SiGe HBT npn achieves 15–30 V/µm of npn width. Second, the BiCMOS SiGe ESD clamp can be used for negative-power-supply voltage products. A disadvantage of the MOSFET RC-triggered clamp in a single- or dual-well technology is that it cannot be used between V_DD and negative-power-supply V_EE because of MOSFET overstress. Third, in contrast to MOSFET ESD networks, the ESD robustness per unit micron (width) does not decrease with successive rf technology generations. Experimental results from three successive SiGe technologies do not show degradation of ESD robustness.

To evaluate the ESD scaling of a SiGe HBT device, a dimensionless group can be established explaining the relationships among thermal conduction, thermal capacity, failure temperature, pulse width, saturation velocity, maximum electric field condition, and the unity current gain cutoff frequency [52, 62–64]. This analysis shows that the frequency of the SiGe HBT increases as the maximum power decreases. As the device dimensions are scaled to achieve these objectives, the power at which failure occurs will decrease unless doping and material changes are addressed. To produce future high-f_T devices, dimensional scaling, doping concentration, and material changes will be needed. This will entail optimization of concentrations of the base dopant, Ge, and carbon. In the evolution of these HBT devices, the choices made to achieve the BV_CEO and the f_T will influence both the maximum power and ESD robustness.

3. Communications technology design and process development

Although Si/SiGe HBT devices have been proposed for many years, the first practical SiGe devices were fabricated in IBM in the late 1980s, in large part enabled by the development of the ability to grow Si/Ge epitaxial layers at low temperatures using ultrahigh-vacuum chemical vapor deposition (UHV/CVD) [65]. This technique freed device designers to be able to grow arbitrary doping profiles without the constraints of high thermal cycles previously thought necessary for the creation of perfectly crystalline material. This activity has led to substantial improvements in the SiGe HBT over several generations by careful scaling of the epitaxial transistor (ETX) device [66] with changes in the low-temperature epitaxy (LTE) base region through modifications in Ge ramp, boron profile, collector design, and carbon doping.

Decisions for the development of new technologies are initiated by marketplace and circuit design requirements, which in turn determine the choice of a BiCMOS technology. While HBT performance (f_T, f_max, and I_C at peak f_T) is frequently of prime importance for these decisions, attention must be paid to CMOS generation (performance, density, V_CC, ASIC compatibility), passive elements, and current-carrying capability. Further restrictions may be placed on a technology by cost and reliability needs. These technology requirements are generated primarily by the marketplace and individual customer strategy. The IBM technology design methodology has been to drive continuous improvement in performance of HBT, CMOS, interconnection technology, and passive elements. Exploitation of all of these enhancements simultaneously, generally introduced into the IBM SiGe high-performance (HP) technologies, increases process complexity and mask count and, therefore, cost. While this is necessary for a large segment of the BiCMOS marketplace, smaller individual markets can be satisfied with reduced technology features through careful development of analog derivative technologies at a reduced cost.

With improvements in both CMOS performance and passive elements, a major market for rf CMOS is also emerging, with new issues which must be addressed. Smaller chip sizes, a pad-limited total chip area, and the predominance of passive components are layout issues that generally distinguish analog and rf designs from their digital counterparts. At the same time, passive device area and wire-bond pads have not decreased with the reduced lithography dimensions; chip areas remain roughly the same for a given function, even with improved lithography dimensions. Consequently, the economic forces driving reduced lithography in digital CMOS technologies (that is, the tradeoff between the lithography-driven chip cost increase and the ability to obtain more chips on a wafer or more functionality per chip) do not apply in the analog and rf domain.

Digital CMOS trends do not influence analog designs. They are costly, and in many cases digital CMOS changes make analog designs significantly more difficult. For example, metallization trends toward thinner films result in higher inter- and intra-level capacitance (per unit area), thereby compromising the performance of designs that retain device-to-device distances between technology generations. These manufacturing limitations are in addition to analog circuit requirements that make it more difficult to design with reduced supply voltages. The net result from this “nonscaling” is that, when compared to digital CMOS, analog and rf technology roadmaps are less defined. Market and targeted design understanding are critical to defining the best mix of technology elements and dimensions.

IBM has demonstrated leadership in the development of world-class analog bipolar and BiCMOS process technologies since its introduction of the world's first SiGe bipolar technology, SiGe 5E, into production in 1996 [67]. Although this premier technology, intended for early fabrication of wireless circuits, did not include all CMOS elements, subsequent high-performance (SiGe HP) technologies have all been fully compatible with corresponding ASIC CMOS technology, resulting in the ability to integrate large amounts of both high-performance analog and digital signal processing. The evolution of these SiGe production technologies spanning 0.5-µm, 0.25-µm, and 0.18-µm generations has been through a combination of vertical scaling (improved SiGe epitaxial films and bipolar profiles), horizontal scaling (improved lithography dimensions and overlay), and CMOS innovation (gate lengths, density, and metallization technology). The improvements in SiGe HP technology are illustrated in Figure 21 (shown later). Details of these technologies demonstrate that the primary technological driver in going from SiGe 5HP [68] to 6HP [2] was improvement in CMOS, while the migration to 7HP [3] was driven by bipolar performance and included the addition of Cu BEOL and further substantial improvements in CMOS.

Semiconductor innovations have been introduced into each successive technology in order to meet the requirements of the marketplace for the rapidly growing wireless industry and the need for higher-bandwidth optical networking products. The development of an integrated SiGe BiCMOS technology originates with an understanding of semiconductor requirements imposed by the marketplace. The wireless customer envisioned for SiGe 5HP could be serviced with a cost-competitive CMOS technology (ASIC CMOS 5X) and analog capabilities achieved with a 50-GHz HBT capable of driving speeds for applications in the 2–5-GHz range. HBT and CMOS technologies were successfully merged by sharing a common polysilicon film for both bipolar extrinsic base and CMOS gate structures. This integration method, referred to as base-during-gate (Figure 18), allowed cost-efficient use of films and masking levels and was made possible by the thermal compatibility of early CMOS structures with the rather deep emitter profile developed in the early HBT. It was clear that Ge doping profiles had a profound effect on both HBT performance and strain that could result in decreased circuit yields, so Ge doping was intentionally kept low to facilitate early production learning. Acceptability by the analog marketplace also required the addition of the high-quality passive elements (resistors, capacitors, inductors, etc.) discussed in detail in the preceding section.

Figure 18

SiGe 6HP was developed first for applications used in storage products which require a very large circuit count of high-performance CMOS such as the read-channel chip described in the next section. For these applications, it was necessary to replace the 0.5-µm CMOS of SiGe 5HP with the 0.25-µm CMOS 6SF. The reduced thermal cycle used in this CMOS generation also required a modification of the integration from base-during-gate to an integration methodology, which fabricated the critical emitter–base region of the HBT after CMOS structures were in place [Figure 18(b)]. While this integration requires careful protection of the CMOS gate conductor during the processing of the HBT, and subsequent removal of these protective films, this base-after-gate integration was successful in the decoupling of thermal cycles required for narrow HBT profiles and the CMOS device activation.

While the first two generations of SiGe BiCMOS could successfully service applications up to 10 Gb/s (OC-192 SONET), 40-Gb/s (OC-768) optical networking products require a subs