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Scaling CMOS to the limitVol. 46, No. 2/3, 2002
Order No. G322-0231 |
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This double issue contains fifteen papers which address the challenges of scaling CMOS devices as physical limits are approached. There are papers on CMOS logic technology, including silicon-on-insulator (SOI), and dynamic random-access memory (DRAM) technology, as well as a proposed CMOS-compatible bipolar technology for analog applications. The reliability of the gate dielectric, and the evolution of devices, processes, and materials are addressed, including new device and material options. Progressing from device to system, the issue includes papers on power dissipation in the context of device limits, interconnect scaling, and the question of how to use the billions of transistors projected for future chips. |
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Papers may be viewed by clicking on the title of interest |
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Papers on Scaling CMOS to the limit |
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Preface |
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Paul M. Solomon, Guest Editor |
p. 119 |
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SOI technology for the GHz era |
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G. G. Shahidi |
p. 121 |
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Beyond the conventional transistor |
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H.-S. P. Wong |
p. 133 |
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Maintaining the benefits of CMOS scaling when scaling bogs down |
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E. J. Nowak |
p. 169 |
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Why BiCMOS and SOI BiCMOS? |
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T. H. Ning |
p. 181 |
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Challenges and future directions for the scaling of dynamic random-access memory (DRAM) |
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J. A. Mandelman, R. H. Dennard, G. B. Bronner, J. K. DeBrosse, R. Divakaruni, Y. Li, and C. J. Radens |
p. 187 |
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CMOS design near the limit of scaling |
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Y. Taur |
p. 213 |
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Effect of increasing chip density on the evolution of computer architectures |
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R. Nair |
p. 223 |
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Power-constrained CMOS scaling limits |
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D. J. Frank |
p. 235 |
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Interconnect opportunities for gigascale integration |
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J. D. Meindl, J. A. Davis, P. Zarkesh-Ha, C. S. Patel, K. P. Martin, and P. A. Kohl |
p. 245 |
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Reliability limits for the gate insulator in CMOS technology |
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J. H. Stathis |
p. 265 |
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CMOS scaling beyond the 100-nm node with silicon-dioxide-based gate dielectrics |
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E. Y. Wu, E. J. Nowak, A. Vayshenker, W. L. Lai, and D. L. Harmon |
p. 287 |
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Vertically scaled MOSFET gate stacks and junctions: How far are we likely to go? |
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C. M. Osburn, I. Kim, S. K. Han, I. De, K. F. Yee, S. Gannavaram, S. J. Lee,
C.-H. Lee, Z. J. Luo, W. Zhu, J. R. Hauser, D.-L. Kwong, G. Lucovsky, T. P. Ma, and M. C. Öztürk |
p. 299 |
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Process requirements for continued scaling of CMOS—the need and prospects for atomic-level manipulation |
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P. D. Agnello |
p. 317 |
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Process modeling for future technologies |
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M. E. Law |
p. 339 |
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New insights into carrier transport in n-MOSFETs |
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A. Lochtefeld, I. J. Djomehri, G. Samudra, and D. A. Antoniadis |
p. 347 |
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Preparation of manuscripts for the IBM Journal of Research and Development |
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p. 359 |
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