References

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2. John Cocke and V. Markstein, “The Evolution of RISC Technology at IBM,” IBM J. Res. & Dev. 34, No. 1, 4–11 (January 1990).
3. S. W. White and S. Dhawan, “POWER2: Next Generation of the RISC System/6000 Family,” IBM J. Res. & Dev. 38, No. 5, 493–502 (September 1994).
4. M. T. Vaden, L. J. Merkel, C. R. Moore, T. M. Potter, and R. J. Reese, “Design Considerations for the PowerPC 601 Microprocessor,” IBM J. Res. & Dev. 38, No. 5, 605–620 (September 1994).
5. Mark Papermaster, Robert Dinkjan, Michael Mayfield, Peter Lenk, Bill Ciarfella, Frank O'Connell, and Raymond DuPont, “POWER3: Next Generation 64-bit PowerPC Processor Design,” IBM White Paper, October 1998, available on the World Wide Web at
   http://www-1.ibm.com/servers/eserver/pseries/hardware/whitepapers/power3wp.pdf.
6. John Borkenhagen and Salvatore Storino, “4th Generation 64-bit PowerPC-Compatible Commercial Processor Design,” IBM White Paper, January 1999, available at
   http://www-1.ibm.com/servers/eserver/pseries/hardware/whitepapers/nstar.pdf.
7. John Borkenhagen and Salvatore Storino, “5th Generation 64-bit PowerPC-Compatible Commercial Processor Design,” IBM White Paper, September 1999, available at
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8. J. M. Borkenhagen, R. J. Eickemeyer, R. N. Kalla, and S. R. Kunkel, “A Multithreaded PowerPC Processor for Commercial Servers,” IBM J. Res. & Dev. 44, No. 6, 885–898 (November 2000).
9. F. P. O'Connell and S. W. White, “POWER3: The Next Generation of PowerPC Processors,” IBM J. Res. & Dev. 44, No. 6, 873–884 (November 2000).
10. C. May (Ed.), E. M. Silha, R. Simpson, and H. S. Warren, Jr. (Ed.), The PowerPC Architecture: A Specification for a New Family of RISC Processors, Morgan Kaufmann Publishers, Inc., San Francisco, 1994.
11. E. Leobandung, E. Barth, M. Sherony, S.-H. Lo, R. Schulz, W. Chu, M. Khare, D. Sadana, D. Schepis, R. Bolam, J. Sleight, F. White, F. Assaderaghi, D. Moy, G. Biery, R. Goldblatt, T.-C. Chen, B. Davari, and G. Shahidi, “High-Performance 0.18 µm SOI CMOS Technology,” IEDM Tech Digest, pp. 679–682 (1999).
12. Linley Gwennap, “Speed Kills,” Microprocessor Report, March 8, 1993, p. 3.
13. See for example the results for the SPECint2000 and SPECfp2000 benchmarks available at www.spec.org.
14. D. C. Bossen, A. Kitamorn, K. F. Reick, and M. S. Floyd, “Fault-Tolerant Design of the IBM pSeries 690 System Using POWER4 Processor Technology,” IBM J. Res. & Dev. 46, No. 1, 77–86 (2002, this issue).
15. J. D. Warnock, J. M. Keaty, J. Petrovick, J. G. Clabes, C. J. Kircher, B. L. Krauter, P. J. Restle, B. A. Zoric, and C. J. Anderson, “The Circuit and Physical Design of the POWER4 Microprocessor,” IBM J. Res. & Dev. 46, No. 1, 27–51 (2002, this issue).
16. T.-Y. Yeh and Y. N. Patt, “A Comparison of Dynamic Branch Predictors that Use Two Levels of Branch History,” Proceedings of the 24th Annual ACM/IEEE International Symposium on Microarchitecture, 1993, pp. 257–266.
17. S. McFarling, “Combining Branch Predictors,” Technical Report TN-36, Digital Western Research Laboratory, Palo Alto, CA, June 1993.
18. R. E. Kessler, “The Alpha 21264 Microprocessor,” IEEE Micro 19, No. 2, 24–36 (March–April 1999).
19. P. Y. Chang, E. Hao, and Y. N. Patt, “Target Prediction for Indirect Jumps,” Proceedings of the 24th Annual International Symposium on Computer Architecture, Denver, June 1997, pp. 274–283.
20. C. F. Webb, “Subroutine Call/Return Stack,” IBM Tech. Disclosure Bull. 30, No. 11, 18–20 (April 1988).
21. Frank Ferraiolo, Edgar Cordero, Daniel Dreps, Michael Floyd, Kevin Gower, and Bradley McCredie, “POWER4 Synchronous Wave-Pipelined Interface,” paper presented at the Hot Chips 11 Conference, Palo Alto, August 1999.