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by
C. F. Webb
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References
- IBM, Enterprise Systems Architecture/390 Principles of
Operation, Order No. SA22-7201-03, September 1996; available through IBM
branch offices.
- IBM, z/Architecture Principles of Operation, in press.
- P. Mak, M. A. Blake, C. C. Jones, G. E. Strait, and P. R.
Turgeon,
Shared-Cache Clusters in a System
with a Fully Shared Memory,
IBM J. Res. Develop. 41, No. 4/5,
429448 (1997).
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P. R. Turgeon, P. Mak, M. A. Blake, M. F. Fee, C. B. Ford III, P. J. Meaney, R. Siegler, and W. W. Shen, “The S/390 G5/G6 Binodal Cache,” IBM J. Res. Develop. 43, No. 5/6, 661670 (1999).
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L. Spainhower and T. Gregg, “IBM S/390 Parallel Enterprise Server G5 Fault Tolerance: A Historical Perspective,” IBM J. Res. Develop. 43, No. 5/6, 863874 (1999).
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J. S. Liptay, “Design of the IBM Enterprise System/9000 High-End Processor,” IBM J. Res. Develop. 36, No. 4, 713731 (1992).
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C. F. Webb and J. S. Liptay, “A High-Frequency Custom CMOS S/390 Microprocessor,” IBM J. Res. Develop. 41, No. 4/5, 463473 (1997).
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T. J. Slegel, R. M. Averill III, M. A. Check, B. C. Giamei, B. W. Krumm, C. A. Krygowski, W. H. Li, J. S. Liptay, J. D. McDougall, T. J. McPherson, J. A. Navarro, E. M. Schwarz, K. Shum, and C. F. Webb, “IBM's S/390 G5 Microprocessor Design,” IEEE Micro 19, No. 2, 1223 (1999).
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M. A. Check and T. J. Slegel, “Custom S/390 G5 and G6 Microprocessors,” IBM J. Res. Develop. 43, No. 5/6, 671680 (1999).
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T. Horel and G. Lauterbach, “UltraSPARC-III: Designing Third-Generation 64-Bit Performance,” IEEE Micro 19, No. 3, 7385 (1999).
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K. M. Jackson and K. N. Langston, “IBM S/390 Storage Hierarchy—G5 and G6 Performance Considerations,” IBM J. Res. Develop. 43, No. 5/6, 847854 (1999).
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