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IBM Journal of Research and Development  
Volume 44, Number 6, 2000
Advanced microprocessor design
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A multithreaded PowerPC processor for commercial servers - References

by J. M. Borkenhagen, R. J. Eickemeyer, R. N. Kalla, and S. R. Kunkel

References

  1. http://www.specbench.org.
  2. A. Maynard, C. Donnelly, and B. Olzewski, Contrasting Characteristics and Cache Performance of Technical and Multi-User Commercial Workloads, Proceedings of the International Conference on Architecture Support for Programming Languages and Operating Systems, October 1994, pp. 145­156.
  3. K. Keeton, D. Patterson, Y. He, R. Raphael, and W. Baker, Performance Characterization of a Quad Pentium Pro SMP Using OLTP Workloads, Proceedings of the 25th International Symposium on Computer Architecture, Barcelona, June 1998, pp. 15­26.
  4. L. Barroso, K. Gharachorloo, and E. Bugnion, Memory System Characterization of Commercial Workloads, Proceedings of the 25th International Symposium on Computer Architecture, Barcelona, June 1998, pp. 3­14.
  5. J. Lo, L. Barroso, S. Eggers, K. Gharachorloo, H. Levy, and S. Parekh, An Analysis of Database Workload Performance on Simultaneous Multithreaded Processors, Proceedings of the 25th International Symposium on Computer Architecture, Barcelona, June 1998, pp. 39­50.
  6. A. Agarwal, J. Kubiatowicz, D. Kranz, B.-H. Lim, D. Yeung, G. D'Souza, and M. Parkin, Sparcle: An Evolutionary Design for Large-Scale Multiprocessors, IEEE Micro 10, No. 3, 48­60 (1994).
  7. R. Alverson, D. Callahan, D. Cummings, B. Koblenz, A. Porterfield, and B. Smith, “The Tera Computer System,” Proceedings of the International Conference on Supercomputing, June 1990, pp. 1­6.
  8. R. Eickemeyer, R. Johnson, S. Kunkel, B.-H. Lim, M. Squillante, and C. Wu, “Evaluation of Multithreaded Processors and Thread Switch Policies,” Proceedings of the 1997 International Symposium on High Performance Computing (Springer LNCS 1336), Fukuoka, Japan, November 1997, pp. 75­90.
  9. R. Eickemeyer, R. Johnson, S. Kunkel, S. Liu, and M. Squillante, “Evaluation of Multithreaded Uniprocessors for Commercial Application Environments,” Proceedings of the 23rd International Symposium on Computer Architecture, Philadelphia, May 1996, pp. 203­212.
  10. D. Tullsen, S. Eggers, and H. Levy, “Simultaneous Multithreading: Maximizing On-Chip Parallelism,” Proceedings of the 22nd International Symposium on Computer Architecture, June 1995, pp. 392­403.
  11. J. Borkenhagen and S. Levenstein, “AS/400 64-Bit PowerPC-Compatible Processor Implementation,” Proceedings of the IEEE International Conference on Computer Design, October 1994, pp. 192­196.
  12. S. Storino, A. Aipperspach, J. Borkenhagen, R. Eickemeyer, S. Kunkel, S. Levenstein, and G. Uhlmann, “A Commercial Multi-Threaded RISC Processor,” presented at the 1998 IEEE International Solid-State Circuits Conference, San Francisco, February 1998.
  13. C. Hristea, D. Lenoski, and J. Keen, “Measuring Memory Hierarchy Performance of Cache-Coherent Multiprocessors Using Micro Benchmarks,” Proceedings of Supercomputing '97, November 1997, p. 25.
  14. The PowerPC Architecture, Second Edition, C. May, E. Silha, R. Simpson, and H. Warren, Eds., Morgan Kaufmann Publishers, San Francisco, 1994.
  15. http://www.tpc.org.

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