1. Introduction, motivation, and objectives

Consider, for example, the vacuum electronic tube, which was replaced by the transistor. The tube still exists for a very few applications, whereas the transistor evolved into today's microelectronics with very large scale integration (VLSI) of microprocessors and memories. Optical lithography may become another example: Although still the predominant technology, it will soon reach its fundamental limits and be replaced by a technology yet unknown. Today we are witnessing in many fields the transition from structures of the micrometer scale to those of the nanometer scale, a dimension at which nature has long been building the finest devices with a high degree of local functionality. Many of the techniques we use today are not suitable for the coming nanometer age; some will require minor or major modifications, and others will be partially or entirely replaced. It is certainly difficult to predict which techniques will fall into which category. For key areas in information technology hardware, it is not yet obvious which technology and materials will be used for nanoelectronics and data storage.

In any case, an emerging technology being considered as a serious candidate to replace an existing but limited technology must offer long-term perspectives. For instance, the silicon microelectronics and storage industries are huge and require correspondingly enormous investments, which makes them long-term-oriented by nature. The consequence for storage is that any new technique with better areal storage density than today's magnetic recording [1] should have long-term potential for further scaling, desirably down to the nanometer or even atomic scale.

The only available tool known today that is simple and yet provides these very long-term perspectives is a nanometer sharp tip. Such tips are now used in every atomic force microscope (AFM) and scanning tunneling microscope (STM) for imaging and structuring down to the atomic scale. The simple tip is a very reliable tool that concentrates on one functionality: the ultimate local confinement of interaction.

In the early 1990s, Mamin and Rugar at the IBM Almaden Research Center pioneered the possibility of using an AFM tip for readback and writing of topographic features for the purposes of data storage. In one scheme developed by them [2], reading and writing were demonstrated with a single AFM tip in contact with a rotating polycarbonate substrate. The data were written thermomechanically via heating of the tip. In this way, densities of up to 30 Gb/in.² were achieved, representing a significant advance compared to the densities of that day. Later refinements included increasing readback speeds to a data rate of 10 Mb/s [3] and implementation of track servoing [4].

In making use of single tips in AFM or STM operation for storage, one must deal with their fundamental limits for high data rates. At present, the mechanical resonant frequencies of the AFM cantilevers limit the data rates of a single cantilever to a few Mb/s for AFM data storage [5, 6], and the feedback speed and low tunneling currents limit STM-based storage approaches to even lower data rates.

Currently a single AFM operates at best on the microsecond time scale. Conventional magnetic storage, however, operates at best on the nanosecond time scale, making it clear that AFM data rates have to be improved by at least three orders of magnitude to be competitive with current and future magnetic recording.

The objectives of our research activities within the Micro- and Nanomechanics Project at the IBM Zurich Research Laboratory are to explore highly parallel AFM data storage with areal storage densities far beyond the expected superparamagnetic limit (60­100 Gb/in.²) [7] and data rates comparable to those of today's magnetic recording.

The “Millipede” concept presented here is a new approach for storing data at high speed and with an ultrahigh density. It is not a modification of an existing storage technology, although the use of magnetic materials as storage media is not excluded. The ultimate locality is given by a tip, and high data rates are a result of massive parallel operation of such tips. Our current effort is focused on demonstrating the Millipede concept with areal densities up to 500 Gb/in.² and parallel operation of very large 2D (32 × 32) AFM cantilever arrays with integrated tips and write/read storage functionality.

The fabrication and integration of such a large number of mechanical devices (cantilever beams) will lead to what we envision as the VLSI age of micro- and nanomechanics. It is our conviction that VLSI micro/nanomechanics will greatly complement future micro- and nanoelectronics (integrated or hybrid) and may generate applications of VLSI­Nano(Micro) ElectroMechanical Systems [VLSI­N(M)EMS] not conceived of today.

2. The Millipede concept

Figure 1

During the storage operation, the chip is raster-scanned over an area called the storage field by a magnetic x/y scanner. The scanning distance is equivalent to the cantilever x/y pitch, which is currently 92 µm. Each cantilever/tip of the array writes and reads data only in its own storage field. This eliminates the need for lateral positioning adjustments of the tip to offset lateral position tolerances in tip fabrication. Consequently, a 32 × 32 array chip will generate 32 × 32 (1024) storage fields on an area of less than 3 mm × 3 mm. Assuming an areal density of 500 Gb/in.², one storage field of 92 µm × 92 µm has a capacity of about 10 Mb, and the entire 32 × 32 array with 1024 storage fields has a capacity of about 10 Gb on 3 mm × 3 mm. As shown in Section 7, the storage capacity scales with the number of elements in the array, cantilever pitch (storage-field size) and areal density, and depends on the application requirements. Although not yet investigated in detail, lateral tracking will also be performed for the entire chip, with integrated tracking sensors at the chip periphery. This assumes and requires very good temperature control of the array chip and the medium substrate between write and read cycles. For this reason the array chip and medium substrate should be held within about 1°C operating temperature for bit sizes of 30 to 40 nm and array chip sizes of a few millimeters. This will be achieved by using the same material (silicon) for both the array chip and the medium substrate in conjunction with four integrated heat sensors that control four heaters on the chip to maintain a constant array-chip temperature during operation. True parallel operation of large 2D arrays results in very large chip sizes because of the space required for the individual write/read wiring to each cantilever and the many I/O pads. The row and column time-multiplexing addressing scheme implemented successfully in every DRAM is a very elegant solution to this issue. In the case of Millipede, the time-multiplexed addressing scheme is used to address the array row by row with full parallel write/read operation within one row.

The current Millipede storage approach is based on a new thermomechanical write/read process in nanometer-thick polymer films. As previously noted, thermomechanical writing in polycarbonate films and optical readback were first investigated and demonstrated with a single cantilever by Mamin and Rugar [2]. Although the storage density of 30 Gb/in.² obtained originally was not overwhelming, the results encouraged us to use polymer films as well to achieve density improvements.

3. Thermomechanical AFM data storage

This situation can be improved if the thermal conductivity of the substrate is increased, and if the depth of tip penetration is limited. We have explored the use of very thin polymer layers deposited on Si substrates to improve these characteristics [12, 13], as illustrated in Figure 2. The hard Si substrate prevents the tip from penetrating farther than the film thickness allows, and it enables more rapid transport of heat away from the heated region because Si is a much better conductor of heat than the polymer. We have coated Si substrates with a 40-nm film of polymethylmethacrylate (PMMA) and achieved bit sizes ranging between 10 and 50 nm. However, we noticed increased tip wear, probably caused by the contact between Si tip and Si substrate during writing. We therefore introduced a 70-nm layer of cross-linked photoresist (SU-8) between the Si substrate and the PMMA film to act as a softer penetration stop that avoids tip wear but remains thermally stable.

Figure 2

Using this layered storage medium, data bits 40 nm in diameter have been written, as shown in Figure 3. These results were obtained using a 1-µm-thick, 70-µm-long, two-legged Si cantilever [11]. The cantilever legs are made highly conducting by high-dose ion implantation, whereas the heater region remains low-doped. Electrical pulses 2 µs in duration were applied to the cantilever with a period of 50 µs. Figure 3(a) demonstrates that 40-nm bits can be written with 120-nm pitch, or very close to each other, without merging [Figure 3(b)], implying a potential bit areal density of 400 Gb/in.²

Figure 3

Imaging and reading are done using a new thermomechanical sensing concept [14]. The heater cantilever originally used only for writing was given the additional function of a thermal readback sensor by exploiting its temperature-dependent resistance. The resistance (R) increases nonlinearly with heating power/temperature from room temperature to a peak value of 500­700°C. The peak temperature is determined by the doping concentration of the heater platform, which ranges from 1 × 10¹⁷ to 2 × 10¹⁸. Above the peak temperature, the resistance drops as the number of intrinsic carriers increases because of thermal excitation [15]. For sensing, the resistor is operated at about 350°C, a temperature that is not high enough to soften the polymer, as is necessary for writing. The principle of thermal sensing is based on the fact that the thermal conductance between the heater platform and the storage substrate changes according to the distance between them. The medium between a cantilever and the storage substrate—in our case air—transports heat from one side to the other. When the distance between heater and sample is reduced as the tip moves into a bit indentation, the heat transport through air will be more efficient, and the heater's temperature and hence its resistance will decrease. Thus, changes in temperature of the continuously heated resistor are monitored while the cantilever is scanned over data bits, providing a means of detecting the bits. Figure 4 illustrates this concept. Under typical operating conditions, the sensitivity of thermomechanical sensing is even better than that of piezoresistive-strain sensing, which is not surprising because thermal effects in semiconductors are stronger than strain effects. The good R/R sensitivity of about 10^­5/nm is demonstrated by the images of the 40-nm-size bit indentations in Figure 3, which were obtained using the described thermal-sensing technique.

Figure 4

In addition to ultradense thermomechanical write/read, we have also demonstrated for the first time the erasing and rewriting capabilities of polymer storage media [12]. Thermal reflow of storage fields is achieved by heating the medium to about 150°C for a few seconds. The smoothness of the reflowed medium allowed multiple rewriting of the same storage field. This erasing process does not allow bit-level erasing; it will erase larger storage areas. However, in most applications single-bit erasing is not required anyway, because files or records are usually erased as a whole.

The erasing and multiple rewriting processes, as well as bit-stability investigations, are topics of ongoing research.

4. Array design, technology, and fabrication

The chip has been used to demonstrate x/y/z scanning and approaching of the entire array, as well as parallel operation for imaging. This was the first parallel imaging by a 2D AFM array chip with integrated piezoresistive deflection sensing. Details of the all-dry micromachining process for the fabrication of the 5 × 5 array and parallel imaging results are described in [10]. The imaging results also confirmed the global chip-approaching and -leveling scheme, since all 25 tips approached the medium within less than 1 µm of z-actuation. Unfortunately, the chip was not able to demonstrate parallel writing because of electromigration problems due to temperature and current density in the Al wiring of the heater. However, we learned from this 5 × 5 test vehicle that 1) global chip approaching and leveling is possible and promising, and 2) metal (Al) wiring on the cantilevers should be avoided to eliminate electromigration and cantilever deflection due to bimorph effects while heating.

Encouraged by the results of the 5 × 5 cantilever array, we designed and fabricated a 32 × 32 array chip. With the findings from the fabrication and operation of the 5 × 5 array and the very dense thermomechanical writing/reading in thin polymers with single cantilevers, we made some important changes in the chip functionality and fabrication processes. The major differences are 1) surface micromachining to form cantilevers at the wafer surface, 2) all-silicon cantilevers, 3) thermal instead of piezoresistive sensing, and 4) first- and second-level wiring with an insulating layer for a multiplexed row/column-addressing scheme.

Since the heater platform functions as a write/read element and no individual cantilever actuation is required, the basic array cantilever cell becomes a simple two-terminal device addressed by multiplexed x/y wiring, as shown in Figure 5. The cell area and x/y cantilever pitchis 92 µm × 92 µm, which results in a total array size of less than 3 mm × 3 mm for the 1024 cantilevers. The cantilever is fabricated entirely of silicon for good thermal and mechanical stability. It consists of the heater platform with the tip on top, the legs acting as a soft mechanical spring, and an electrical connection to the heater. They are highly doped to minimize interconnection resistance and replace the metal wiring on the cantilever to eliminate electromigration and parasitic z-actuation of the cantilever due to the bimorph effect. The resistive ratio between the heater and the silicon interconnection sections should be as high as possible; currently the highly doped interconnections are 400 and the heater platform is 11 k (at 4 V reading bias).

Figure 5

The cantilever mass must be minimized to obtain soft (flexible), high-resonant-frequency cantilevers. Soft cantilevers are required for a low loading force in order to eliminate or reduce tip and medium wear, whereas a high resonant frequency allows high-speed scanning. In addition, sufficiently wide cantilever legs are required for a small thermal time constant, which is partly determined by cooling via the cantilever legs [11]. These design considerations led to an array cantilever with 50-µm-long, 10-µm-wide, 0.5-µm-thick legs, and a 5-µm-wide, 10-µm-long, 0.5-µm-thick platform. Such a cantilever has a stiffness of 1 N/m and a resonant frequency of 200 kHz. The heater time constant is a few microseconds, which should allow a multiplexing rate of 100 kHz.

The tip height should be as small as possible because the heater platform sensitivity depends strongly on the distance between the platform and the medium. This contradicts the requirement of a large gap between the chip surface and the storage medium to ensure that only the tips, and not the chip surface, are making contact with the medium. Instead of making the tips longer, we purposely bent the cantilevers a few micrometers out of the chip plane by depositing a stress-controlled plasma-enhanced chemical vapor deposition (PECVD) silicon-nitride layer at the base of the cantilever (see Figure 5). This bending as well as the tip height must be well controlled in order to maintain an equal loading force for all cantilevers of an array.

Cantilevers are released from the crystalline Si substrate by surface micromachining using either plasma or wet chemical etching to form a cavity underneath the cantilever. Compared to a bulk-micromachined through-wafer cantilever-release process, as performed for our 5 × 5 array [10], the surface-micromachining technique allows an even higher array density and yields better mechanical chip stability and heat sinking. Because the Millipede tracks the entire array without individual lateral cantilever positioning, thermal expansion of the array chip must be either small or well-controlled. Because of thermal chip expansion, the lateral tip position must be controlled with better precision than the bit size, which requires array dimensions as small as possible and a well-controlled chip temperature. For a 3 mm × 3 mm silicon array area and 10-nm tip-position accuracy, the chip temperature has to be controlled to about 1°C. This is ensured by four temperature sensors in the corners of the array and heater elements on each side of the array. Thermal expansion considerations were a strong argument for the 2D array arrangement instead of 1D, which would have made the chip 32 times longer for the same number of cantilevers.

The photograph in Figure 6 shows a fabricated chip with the 32 × 32 array located in the center (3 mm × 3 mm) and the electrical wiring interconnecting the array with the bonding pads at the chip periphery.

Figure 6

Figure 7 shows the 32 × 32 array section of the chip with the independent approach/heat sensors in the four corners and the heaters on each side of the array, as well as zoomed scanning electron micrographs (SEMs) of an array section, a single cantilever, and a tip apex. The tip height is 1.7 µm and the apex radius is smaller than 20 nm, which is achieved by oxidation sharpening [16].

Figure 7

The cantilevers are interconnected by integrating Schottky diodes in series with the cantilevers. The diode is operated in reverse bias (high resistance) if the cantilever is not addressed, thereby greatly reducing crosstalk between cantilevers. More details about the array fabrication are given in Reference [17].

5. Array characterization

Figure 8

In the low-power, low-temperature regime, silicon mobility is affected by phonon scattering, which depends on temperature, whereas at higher power the intrinsic temperature of the semiconductor is reached, resulting in a resistivity drop due to the increasing number of carriers [15]. Depending on the heater-platform doping concentration of 1 × 10¹⁷ to 2 × 10¹⁸ at./cm³, our calculations estimate a resistance maximum at temperatures of 500°C and 700°C, respectively.

The cantilevers within the array are electrically isolated from one another by integrated Schottky diodes. Because every parasitic path in the array to the addressed cantilever of interest contains a reverse-biased diode, the crosstalk current is drastically reduced, as shown in Figure 9. Thus, the current response to an addressed cantilever in an array is nearly independent of the size of the array, as demonstrated by the I/V curves in Figure 9. Hence, the power applied to address a cantilever is not shunted by other cantilevers, and the reading sensitivity is not degraded—not even for very large arrays (32 × 32). The introduction of the electrical isolation using integrated Schottky diodes turned out to be crucial for the successful operation of interconnected cantilever arrays with a simple time-multiplexed addressing scheme. Figure 10 shows the measured cantilever resistance uniformity across the array for both forward- and reverse-biased diodes. Good uniformity is essential for a robust write/read electronics design.

Figure 9 Figure 10

The tip-apex height uniformity within an array is very important because it determines the force of each cantilever while in contact with the medium and hence influences write/read performance as well as medium and tip wear. Wear investigations suggest that a tip-apex height uniformity across the chip of less than 500 nm is required [4], with the exact number depending on the spring constant of the cantilever. In the case of the Millipede, the tip-apex height is determined by the tip height and the cantilever bending. Figure 11 shows the tip-apex height uniformity of one row of the array (32 tips) due to tip height and cantilever bending. It demonstrates that our uniformity is of the order of 100 nm, thus meeting requirements.

Figure 11

6. First write/read results with the 32 x 32 array chip

We have explored two x/y/z scanning approaching schemes to operate the array for writing/reading. The first one is based closely on the Millipede basic concept shown in Figure 1. A 3 mm × 3 mm silicon substrate is spin-coated with the SU-8/PMMA polymer medium structure described in Section 3. This storage medium is attached to a small magnetic x/y/z scanner and approaching device. The three magnetic z-approaching actuators bring the medium into contact with the tips of the array chip. The z-distance between the medium and the Millipede chip is controlled by the approaching sensors (additional cantilevers) in the corners of the array. The signals from these cantilevers are used to determine the forces on the z-actuators and, hence, also the forces of the cantilever while it is in contact with the medium. This sensing and actuation feedback loop continues to operate during x/y scanning of the medium. The PC-controlled write/read scheme addresses the 32 cantilevers of one row in parallel. Writing is performed by connecting the addressed row for 20 µs to a high, negative voltage and simultaneously applying data inputs (“0” or “1”) to the 32 column lines. The data input is a high, positive voltage for a “1” and ground for a “0.” This row-enabling and column-addressing scheme supplies a heater current to all cantilevers, but only those cantilevers with high, positive voltage generate an indentation (“1”). Those with ground are not hot enough to make an indentation, and thus write a “0.” When the scan stage has moved to the next bit position, the process is repeated, and this is continued until the line scan is finished. In the read process, the selected row line is connected to a moderate negative voltage, and the column lines are grounded via a protection resistor of about 10 k, which keeps the cantilevers warm. During scanning, the voltages across the resistors are measured. If one of the cantilevers falls into a “1” indentation, it cools, thus changing the resistance and voltage across the series resistor. The written data bit is sensed in this manner.

The SEM and the AFM image in Figure 12 show our first parallel writing/reading results. Figure 12(a) shows a SEM image of a large area of the polymer medium, in which the many small bright spots indicate the location of storage fields with data written by the corresponding cantilevers. The data written consisted of an IBM logo composed of indentations (“1”s) and clear separations (“0”s). Figure 12(b) shows magnified images of two storage fields. The dots are about 50 nm in diameter, which results in areal densities of 100­200 Gb/in.² depending on the ability to separate the bit indentations by a distinguishable amount. A first successful attempt demonstrates the read-back of the stored data by the integrated thermomechanical sensing: Figure 12(c) shows the raw read-back data of two different storage fields with areal density similar to that in 12(b). Figure 13 is a photograph of the complete experimental Millipede setup.

Figure 12 Figure 13

The second x/y/z scanning and approaching system we explored, illustrated in Figure 14(a), makes use of a modified magnetic hard-disk drive. The array chip replaced the magnetic write/read head slider and was mechanically leveled and fixed on the suspension arm. The z-approaching and -contacting procedure was performed by a piezoelectric actuator mounted on top of the suspension, which brought the array chip into contact with the medium and maintained it there. The 92-µm scanning in x was achieved by the standard voice-coil actuator of the suspension arm, whereas the y-scanning was performed by the slowly moving disk. The row/column-addressing scheme is very similar to the one used for the x/y/z scanner. The first writing results are shown by the SEM images in Figures 14(b) and 14(c). The bright lines in Figure 14(b) again identify the locations of the storage fields written by many cantilevers with 92-µm pitch in each direction, whereas Figure 14(c) shows the bit indentations of one storage field corresponding to 70­100 Gb/in.² This lower areal density is primarily due to the thicker PMMA layer (100 nm) used for this experiment. Reading operation is currently being investigated.

Figure 14

7. Discussion of possible Millipede applications in data storage

Figure 15

•   Small-form-factor storage system (Nanodrive)
IBM's recent product announcement of the Microdrive represents a first successful step into miniaturized storage systems. As we enter the age of pervasive computing, we can assume that computer power is available virtually everywhere. Miniaturized and low-power storage systems will become crucial, particularly for mobile applications. The availability of storage devices with gigabyte capacity having a very small form factor (in the range of centimeters or even millimeters) will open up new possibilities to integrate such “Nanodrives” into watches, cellular telephones, laptops, etc., provided such devices have low power consumption.

We have recently demonstrated that the magnetic x/y/z scanner can be micromachined and miniaturized [18, 19] with potential for even further miniaturization. Figure 16(a) shows the basic principles of the integrated micromagnetic scanner concept, whereas Figure 16(b) is a photograph of the first micromachined silicon scanner. Further details on the design and fabrication have been published in References [18, 19].

Figure 16

The array chip with integrated or hybrid electronics and the micromagnetic scanner are key elements demonstrated for a Millipede-based device called Nanodrive, which is of course also very interesting for audio and video consumer applications. All-silicon, batch fabrication, low-cost polymer media, and low power consumption make Millipede very attractive as a centimeter- or even millimeter-sized gigabyte storage system.

•   Terabit drive
The potential for very high areal density renders the Millipede also very attractive for high-end terabit storage systems. As mentioned above, terabit capacity can be achieved with three Millipede-based approaches: 1) very large arrays, 2) many smaller arrays operating in parallel, and 3) displacement of small/medium-sized arrays over large media.

Although the fabrication of considerably larger arrays (10⁵ to 10⁶ cantilevers) appears to be possible, control of the thermal linear expansion will pose a considerable challenge as the array chip becomes significantly larger. The second approach is appealing because the storage system can be upgraded to fulfill application requirements in a modular fashion by operating many smaller Millipede units in parallel. The operation of the third approach was described above with the example of a modified hard disk. This approach combines the advantage of smaller arrays with the displacement of the entire array chip, as well as repositioning of the polymer-coated disk to a new storage location on the disk. A storage capacity of several terabits appears to be achievable on 2.5- and 3.5-in. disks. In addition, this approach is an interesting synergy of existing, reliable (hard-disk drive) and new (Millipede) technologies.

8. Summary and outlook

The current Millipede array chip fabrication technique is compatible with CMOS circuits, which will allow future microelectronics integration. This is expected to produce better performance (speed) and smaller system form factors, as well as lower costs.

Although we have demonstrated the first high-density storage operations with the largest 2D AFM array chip ever built, a number of issues must be addressed before the Millipede can be considered for commercial applications; a few of these are listed below:

• Overall system reliability, including bit stability, tip and medium wear, erasing/rewriting.
• Limits of data rate (S/N ratio), areal density, array and cantilever size.
• CMOS integration.
• Optimization of write/read multiplexing scheme.
• Array-chip tracking.

Our near-term future activities are focused on these important aspects.

Finally, we would like to conclude with some thoughts and visions on the long-term outlook for the Millipede concept.

The highly parallel nanomechanical approach is novel in many respects. Recalling the transistor-to-microprocessor story mentioned at the beginning, we might ask whether a new device of a yet inconceivable level of novelty could possibly emerge from the Millipede. There is at least one feature of the Millipede that we have not yet exploited. With integrated Schottky diodes and the temperature-sensitive resistors on the current version of the Millipede array chip, we have already achieved the first and simplest level of micromechanical/electronic integration, but we are looking for much more complex ones to make sensing and actuation faster and more reliable. However, we envision something very much beyond this. Whenever there is parallel operation of functional units, there is the opportunity for sophisticated communication or logical interconnections between these units. The topology of such a network carries its own functionality and intelligence that goes beyond that of the individual devices. It could, for example, act as a processor. For the Millipede this could mean that a processor and VLSI­nanomechanical device may be merged to form a “smart” Millipede. We do not completely foresee what this could ultimately mean, but we do have a vision of the direction in which to go. If the Millipede is used, for example, as an imaging device, let us say for quality control in silicon chip fabrication, the amount of information it can generate is so huge that it is difficult to transmit these data to a computer to store and process them. Furthermore, most of the data are not of interest at all, so it would make sense if only the pertinent parts were predigested by the specialized smart Millipede and then transmitted. For this purpose, communication between the cantilevers is helpful because a certain local pattern detected by a single tip can mean something in one context and something else or even nothing in another context. The context might be derived from the patterns observed by other tips. A similar philosophy could apply to the Millipede as a storage device. A smart Millipede could possibly find useful pieces of information very quickly by a built-in complex pattern recognition ability, e.g., by ignoring information when certain bit patterns occur within the array. The bit patterns are recognized instantaneously by logical interconnections of the cantilevers. Even with this somewhat vague vision, we are very confident that the “smart” Millipede will have interesting long-term prospects in many application fields, possibly in fields that we cannot even envision today.

9. Acknowledgments

References

Received August 17, 1999; accepted for publication November 22, 1999