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IBM Journal of Research and Development  
Volume 44, Number 3, 2000
Directions in information technology
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The future of interconnection technology - References

by T. N. Theis

References

  1. C. W. Kaanta, W. J. Cote, J. E. Cronin, K. L. Holland, P. I. Lee, and T. M. Wright, “Submicron Wiring Technology with Tungsten and Planarization,” Proc. IEEE IEDM, pp. 209­212 (1987).
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  3. J. G. Ryan, R. M. Geffken, N. R. Poulin, and J. R. Paraszczak, “The Evolution of Interconnection Technology at IBM,” IBM J. Res. Develop. 39, 371 (1995).
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  5. H. B. Bakoglu, Circuits, Interconnections, and Packaging for VLSI, Addison-Wesley Publishing Co., Inc., Reading, MA, 1990, pp. 202­204.
  6. Ibid., p. 197.
  7. S. Yang, S. Ahmed, B. Arcot, R. Arghavani, P. Bai, S. Chambers, P. Charvat, R. Cotner, R. Gasser, T. Ghani, M. Hussein, C. Jan, C. Kardas, J. Maiz, P. McGregor, B. McIntyre, P. Nguyen, P. Packan, I. Post, S. Sivakumar, J. Steigerwald, M. Taylor, B. Tufts, S. Tyagi, and M. Bohr, “A High Performance 180 nm Generation Logic Technology,” Proc. IEEE IEDM, pp. 197­200 (1998).
  8. Bakoglu, op. cit., p. 140.
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  12. H. B. Bakoglu and J. D. Meindl, “Optimal Interconnection Circuits for VLSI,” IEEE Trans. Electron Devices ED-32, 903 (1985).
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  15. The National Technology Roadmap for Semiconductors: Technology Needs, Semiconductor Industry Association, 1997, pp. 101­102.
  16. T. N. Theis, “Challenges in the Extension of Hierarchical Wiring Systems,” Electrochemical Processing in ULSI Fabrication I and Interconnect and Contact Metallization: Materials, Processes, and Reliability, Vol. 98-6, P. C. Andricacos, J. O. Dukovic, G. S. Mathad, G. M. Oleszek, H. S. Rathore, and C. Reidsema Simpson, Eds., The Electrochemical Society, Inc., Pennington, NJ, 1999, pp. 1­11.
  17. W. E. Donath, “Wire Length Distribution for Placements of Computer Logic,” IBM J. Res. Develop. 25, 152 (1981).
  18. J. A. Davis, V. K. De, and J. D. Meindl, “A Stochastic Wire-Length Distribution for Gigascale Integration (GSI)—Part I: Derivation and Validation,” IEEE Trans. Electron Devices 45, 580 (1998).
  19. Bakoglu, op. cit., p. 214.
  20. D. A. B. Miller, “Dense Two-Dimensional Integration of Optoelectronics and Electronics for Interconnections,” Heterogeneous Integration: Systems on a Chip, A. Husain and M. Fallahi, Eds., SPIE Critical Reviews of Optical Engineering, Vol. CR70, SPIE, Bellingham, WA, 1998, pp. 80­109 and references therein.
  21. D. A. B. Miller, “Physical Reasons for Optical Interconnection,” Int. J. Optoelectron. 11, 155 (1997).
  22. A. Deutsch, H. Harrer, C. W. Surovic, G. Hellner, D. C. Edelstein, R. D. Goldblatt, G. A. Biery, N. A. Greco, D. M. Foster, E. Crabbe, L. T. Su, and P. W. Coteus, “Functional High-Speed Characterization and Modeling of a Six-Layer Copper Wiring Structure and Performance Comparison with Aluminum On-Chip Interconnections,” Proc. IEEE IEDM, 1998, pp. 295­298.
  23. J. D. Joannopoulos, R. D. Meade, and J. N. Winn, Photonic Crystals, Princeton University Press, New York, 1995; J. D. Joannopoulos, P. R. Villeneuve, and S. Fan, “Photonic Crystals: Putting a New Twist on Light,” Nature 386, 143­149 (1997).
  24. D. A. B. Miller and H. M. Ozaktas, “Limit to the Bit-Rate Capacity of Electrical Interconnects from the Aspect Ratio of the System Architecture,” J. Parallel Distr. Computing 41, 42 (1997).
  25. S. Fan, P. R. Villeneuve, J. D. Joannopoulos, and H. A. Haus, “Channel Drop Tunneling Through Localized States,” Phys. Rev. Lett. 80, 960 (1997).
  26. S. Keckler and W. Dally, “Processor Coupling: Integrating Compile-Time and Run-Time Parallelism,” Proceedings of the 19th Annual International Symposium on Computer Architecture, 1992, pp. 202­213.
  27. W. J. Dally, “Interconnect-Limited VLSI Architecture,” Proceedings of the 1999 International Interconnect Technology Conference, San Francisco, May 24­26, 1999, pp. 15­17.
  28. http://fcrp.src.org.

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