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IBM Journal of Research and Development  
Volume 43, Numbers 5/6, 1999
IBM S/390 Server G5/G6
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PLL modeling and verification in a cycle-simulation environment - Author bios

by G. A. Van Huben, T. G. McNamara, and T. E. Gilbert

Biographical sketches of authors

Gary A. Van Huben   IBM System/390 Division, 522 South Road, Poughkeepsie, New York 12601 (vanhuben@us.ibm.com). Mr. Van Huben joined IBM in 1986 and is currently an Advisory Engineer. He has held various design assignments involving the S/390 storage controller, central processor, and I/O subsystem. His most recent assignment is overall responsibility for the Level 2 cache and subsystem data flow. In addition to logic design, Mr. Van Huben has also worked on various design processes and methodologies within the S/390 organization, including his present position as technical leader for the data management and design control process governing S/390 hardware design. Mr. Van Huben received his B.S. degree in electrical and computer engineering from Clarkson University in 1986; he currently holds seven U.S. patents, has received three IBM Invention Achievement Plateau Awards, and has authored several technical papers.

Timothy G. McNamara   IBM System/390 Division, 522 South Road, Poughkeepsie, New York 12601 (tmcnamar@us.ibm.com). Mr. McNamara is a Senior Engineer in S/390 custom microprocessor design. He received his B.E. degree in electrical engineering from the State University of New York at Stony Brook in 1983 and his M.S. degree in computer engineering from Syracuse University in 1990. He is currently working on high-performance clock system designs for the S/390 CMOS microprocessors. Mr. McNamara has authored or co-authored a number of technical papers; he holds three U.S. patents.

Thomas E. Gilbert   IBM System/390 Division, 522 South Road, Poughkeepsie, New York 12601 (tgilbert@us.ibm.com). Mr. Gilbert joined IBM in 1974 and has held many technical and management positions. He is currently an Advisory Engineer in IBM S/390 design verification, working on the CMOS clock chip and system integration of the S/390 G5 system. His previous verification experience includes team leader and verification of areas on various S/390 systems and CMOS channels. He has been working in design verification since 1984. Mr. Gilbert received an IBM Outstanding Innovation Award in 1988 for his work on I/O subsystem drivers, an IBM Outstanding Technical Achievement Award in 1990 for his work on scan-ring modeling, and an IBM Team Award for his work on the S/390 G3 common chip verification. Most recently he has received IBM Outstanding Innovation Awards for his clock chip and LBIST verification on S/390 G4 and G5.