Biographical sketches of authors
Paul R. Turgeon
IBM System/390 Division, 522 South Road, Poughkeepsie, New York 12601 (turgeon@us.ibm.com).
Mr. Turgeon is currently the manager of S/390 I/O and Connectivity Development. During the development of the S/390 G5 and G6 servers, he had design and project management responsibility for the high-performance cache, memory hierarchy, and processor subsystem designs described here. He has held various design and design management positions on the IBM 8100 Information System, ES/3090, ES/9121, and the S/390 G4, G5, and G6 systems, and has received several IBM formal awards including Outstanding Technical Achievement Awards for both the G4 and G5 designs. He holds a B.S. in electrical engineering from Rensselaer Polytechnic Institute (1979) and a Master’s Certificate in project management from George Washington University (1996).
Pak-kin Mak
IBM System/390 Division, 522 South Road, Poughkeepsie, New York 12601 (pmak@us.ibm.com).
Mr. Mak is a Senior Technical Staff Member in S/390 Custom Hardware Design. He received his B.S.E.E. degree from Polytechnic Institute of New York and his M.B.A. degree from Union College. Mr. Mak joined IBM Poughkeepsie in 1981, working on the ES/3090 BCE cache design. He has designed high-end system controllers and L2 caches for ES/9021 bipolar-based systems and was the technical team leader for the S/390 G4, G5, and G6 shared L2 cache designs. Mr. Mak currently holds three patents and has received three IBM Invention Achievement Awards, two IBM Outstanding Innovation Awards, two IBM Outstanding Technical Achievement Awards, and two Division Awards.
Michael A. Blake
IBM System/390 Division, 522 South Road, Poughkeepsie, New York 12601 (mablake@us.ibm.com).
Mr. Blake is an Advisory Engineer in S/390 Custom Hardware Design. He was the SC Chip Logic Team Leader for the G5 and G6 systems. In addition, he designed the internode controllers used in these systems. He previously held design positions on the IBM ES/3090, ES/9021, and S/390 G4 systems. He has received several IBM formal awards, including an Outstanding Technical Achievement Award for the G4 design and an Outstanding Innovation Award for the G5 design. Mr. Blake holds one U.S. patent and has three patents pending. He holds a B.S. in electrical engineering from Rensselaer Polytechnic Institute (1981).
Michael F. Fee
IBM System/390 Division, 522 South Road, Poughkeepsie, New York 12601 (fee@us.ibm.com).
Mr. Fee is an Advisory Engineer in S/390 Custom Hardware Design. He was the primary designer of the G5 system controller’s microprocessor controller, cross invalidate, and store buffering functions. He developed and implemented logic synthesis and timing methodologies for the SC and L2 cache chips, and was responsible for achieving required cycle time targets. He has received IBM Outstanding Technical Achievement Awards for his contributions to the G4 and G5 products, and has three patents pending. Mr. Fee has worked exclusively on shared-cache system designs for IBM since receiving his B.S. in electrical engineering from Manhattan College (1989).
Carl B. Ford III
IBM System/390 Division, 522 South Road, Poughkeepsie, New York 12601 (carl_ford@vnet.ibm.com).
Mr. Ford is an Advisory Engineer in the S/390 development organization. He received his B.S. in electrical engineering from Rutgers University in 1983. Since joining IBM in Poughkeepsie, New York, in 1983, he has worked on processor controller code and logic design for the ES/3090 and ES/9021 bipolar mainframes and logic design for the S/390 G4, G5, and G6 CMOS mainframes. Mr. Ford was responsible for the hardware-assisted move engine and numerous other controller functions. He holds one patent and has received an IBM Invention Achievement Award and three Outstanding Technical Achievement Awards.
Patrick J. Meaney
IBM System/390 Division, 522 South Road, Poughkeepsie, New York 12601 (meaney@us.ibm.com).
Mr. Meaney is an Advisory Engineer in S/390 Custom Hardware Design. He is the SC/L2 Timing Leader responsible for design and simulation to meet frequency goals. Mr. Meaney is also responsible for definition of SC RAS and recovery features for future S/390 CMOS systems. He was the L2 Cache Chip Design Leader for the G5/G6. Mr. Meaney holds ten U.S. patents and has six patents pending. He has held design positions on the ES/9021 and the S/390 G4, G5, and G6 systems, and has received several IBM formal awards, including an Outstanding Technical Achievement Award for the G4 and an Outstanding Innovation Award for the G5 design. He holds a B.S. in electrical and computer engineering from Clarkson University (1986) and an M.S. in computer engineering from Syracuse University (1991).
Rick Seigler
IBM System/390 Division, 522 South Road, Poughkeepsie, New York 12601 (seigler@us.ibm.com).
Mr. Seigler joined IBM Poughkeepsie in 1980 after receiving B.S.E.E. and M.S.E.E. degrees from Rensselaer Polytechnic Institute. He worked as a Logic Designer and Systems Test Engineer on ES/3090 systems, and as a Recovery/Serviceability Systems Test Manager for ES/3090 and ES/9021 systems. In 1992 he joined S/390 Custom Hardware Design, where he now works as an Advisory Engineer; prior to that, he served one year on an IBM Faculty Loan assignment at the Georgia Institute of Technology in Atlanta. Mr. Seigler holds five patents and has received IBM Outstanding Technical Achievement Awards for his work on the G4 and G5 systems.
William Wu Shen
IBM System/390 Division, 522 South Road, Poughkeepsie, New York 12601 (shen@us.ibm.com).
Dr. Shen is a Senior Engineer in S/390 Custom Hardware Design, currently responsible for memory subsystem architecture and memory controller interface design implementation. He holds eight U.S. patents and has ten patents pending. He joined IBM in 1978 and has held design engineering positions working on the memory subsystems of the IBM 8100 Information System, ES/3090, ES/9021, and S/390 CMOS G4, G5, and G6 systems. Dr. Shen has received several IBM formal awards, including an Outstanding Technical Achievement Award for G4 and an Outstanding Innovation Award for G5. He holds a Master of Science degree (1974) and a Doctor of Science degree (1981), both from Clarkson University. In addition to memory subsystem design, Dr. Shen is also interested in fault-tolerant design, system testing, and performance modeling.
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