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by
P. Song, F. Motika, D. R. Knebel, R. F. Rizzolo, and M. P. Kusko |
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References
-
D. E. Hoffman, R. M. Averill, B. Curran, Y. H. Chan, A. Dansky, R. Hatch, T. McNamara, T. McPherson, G. Northrop, L. Sigal, A. Pelella, and P. M. Williams, Deep Submicron Design Techniques for the 500MHz IBM S/390 G5 Custom Microprocessor, Proceedings of the International Conference on Computer Design, 1998, pp. 258263.
-
W. H. Kautz, Fault Testing and Diagnosis in Combinational Digital Circuits, IEEE Trans. Computers C-18, 352366 (April 1968).
-
S. Y. H. Su and Y. C. Cho, A New Approach to the Fault Location of Combinational Circuits, IEEE Trans. Computers C-21, 2130 (January 1972).
-
Nandakumar N. Tendolkar and Robert L. Swann, Automated Diagnostic Methodology for the IBM 3081 Processor Complex, IBM J. Res. Develop. 26, No. 1, 7888 (January 1982).
-
T. Yano and H. Okamoto, Fast Fault Diagnostic Method Using Fault Dictionary for Electron Beam Tester, Proceedings of the IEEE International Test Conference, September 1987, pp. 561565.
-
M. Abramovici, M. A. Breuer, and A. D. Friedman, Digital Systems Testing and Testable Design, AT&T Bell Laboratories and W. H. Freeman and Company, 1990.
-
F. Hsu, P. Solecky, and R. Beaudoin, Structure Trace Diagnosis for LSSD Board TestingAn Alternative to Full Fault Simulated Diagnosis, Proceedings of the 18th Design Automation Conference, June 1981, pp. 891897.
-
M. Abramovici and M. A. Breuer, Multiple Fault Diagnosis in Combinational Circuits Based on an Effect Cause Analysis, IEEE Trans. Computers C-29, No. 6, 451460 (June 1980).
-
J. A. Waicukauski, V. P. Gupta, and S. T. Patel, Diagnosis of BIST Failures by PPSFP Simulation, Proceedings of the IEEE International Test Conference, September 1987, pp. 480484.
-
H. Cox and J. Rajski, A Method of Fault Analysis for Test Generation and Fault Diagnosis, IEEE Trans. Computer-Aided Design 7, No. 7, 813833 (1988).
-
J. A. Waicukauski and E. Lindbloom, Failure Diagnosis of Structured VLSI, IEEE Design & Test of Computers 5, 4960 (August 1989).
-
TestBench User's Guide, IBM Microelectronics Division, Endicott, NY, November 1996.
-
D. P. Vallet, IC Failure Analysis: The Importance of Test and Diagnostics, IEEE Design & Test of Computers 13, 7682 (July/September 1997).
-
J. C. Tsang and J. A. Kash, Picosecond Hot Electron Light Emission from Submicron Complementary Metal-Oxide-Semiconductor Circuits, Appl. Phys. Lett. 70, No. 7, 889891 (February 1997).
-
J. A. Kash and J. C. Tsang, Dynamic Internal Testing of CMOS Circuits Using Hot Luminescence, IEEE Electron Device Lett. 18, 330 (1997).
-
J. A. Kash, J. C. Tsang, R. F. Rizzolo, A. K. Patel, and A. D. Shore, Backside Optical Emission Diagnostics for Excess IDDQ, IEEE J. Solid-State Circuits 33, No. 3, 508511 (March 1998).
-
D. Knebel, P. Sanda, D. Vallet, L. Huisman, P. Nigh, R. Rizzolo, P. Song, and F. Motika, Diagnosis and Characterization of Timing-Related Defects by Time-Dependent Light Emission, Proceedings of the IEEE International Test Conference, October 1998, pp. 729733.
-
M. Kusko, B. Robbins, T. Snethen, P. Song, T. Foote, and W. Huott, Microprocessor Test and Test Tool Methodology for the 500 MHz IBM S/390 G5 Chip, Proceedings of the IEEE International Test Conference, October 1998, pp. 717726.
-
E. B. Eichelberger, Method of Level Sensitive Testing a Functional Logic System, U.S. Patent 3,761,695, September 25, 1973.
-
E. B. Eichelberger and T. W. Williams, A Logic Design Structure for LSI Testability, Proceedings of the 14th Design Automation Conference, New Orleans, 1977, pp. 462468.
-
Y. Wu and S. Adam, BIST Fault Diagnosis in Scan-Based VLSI Environments, Proceedings of the IEEE International Test Conference, October 1996, pp. 4857.
-
J. Rajski and J. Tyszer, Fault Diagnosis in Scan-Based BIST, Proceedings of the IEEE International Test Conference, November 1997, pp. 894902.
-
P. G. Shephard III, W. Huott, P. R. Turgeon, R. W. Berry, Jr., P. Patel, G. Yasar, J. Hanley, and F. J. Cox, Programmable Built-In Self Test Method and Controller for Arrays, U.S. Patent 5,633,877, May 1996.
-
P. H. Bardell and W. H. McAnney, Self-Testing of Multichip Modules, Proceedings of the IEEE International Test Conference, 1982, pp. 200204.
-
F. Motika and J. Waicukauski, Weighted Random Pattern Testing Apparatus and Method, U.S. Patent 4,688,233, August 18, 1987.
-
J. A. Waicukauski, E. Lindbloom, E. B. Eichelberger, and O. P. Forlenza, A Method for Generating Weighted Random Test Patterns, IBM J. Res. Develop. 33, No. 2, 149161 (March 1989).
-
B. Konemann, J. Barlow, P. Chang, R. Gabrielson, C. Goertz, B. Keler, K. McCauley, J. Tischer, V. Iyenger, B. Rosen, and T. Williams, Delay Test: The Next Frontier for LSSD Test Systems, Proceedings of the IEEE International Test Conference, 1992, pp. 578587.
-
K. Baker and J. V. Beers, Shmoo Plotting; The Black Art of IC Testing, IEEE Design & Test of Computers 13, 9097 (July/September 1997).
-
J. L. Schafer, F. A. Policastri, and R. J. McNulty, Partner SRLs for Improved Shift Register Diagnostics, Proceedings of the IEEE VLSI Test Symposium, 1992, pp. 198201.
-
S. Kundu, Diagnosing Scan Chain Faults, IEEE Trans. VLSI Syst. 2, No. 4, 512516 (December 1994).
-
S. Edirisooriya and G. Edirisooriya, Diagnosis of Scan Path Failures, Proceedings of the IEEE VLSI Test Symposium, April 1995, pp. 250255.
-
S. Narayanan and A. Das, An Efficient Scheme to Diagnose Scan Chains, Proceedings of the IEEE International Test Conference, 1997, pp. 704713.
-
F. Motika, J. J. Shushereba, D. Forlenza, and P. Nigh, Logic BIST Diagnostic Method, IBM Docket BU9-97-022, June 1997.
-
P. Song, F. Motika, M. Kusko, R. Rizzolo, J. Lee, and R. Clairmont, High Resolution Diagnostic Techniques for the IBM S/390 Microprocessor, Proceedings of the 8th IEEE North Atlantic Test Workshop, May 1999, pp. 6775.
-
Wayne Needham, Cheryl Prunty, and Eng Hong Yeoh, High Volume Microprocessor Test Escapes, An Analysis of the Defects Our Tests Are Missing, Proceedings of the IEEE International Test Conference, November 1998, pp. 2534.
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