Biographical sketches of authors
Chitta L. Rao
IBM System/390 Division, 522 South Road, Poughkeepsie, New York 12601 (clrao@us.ibm.com).
Dr. Rao is with the S/390 hardware performance group, working on Parallel Sysplex performance. He received an M.S. degree in electrical engineering from McGill University, Montreal, Canada, and a Ph.D. degree in theoretical nuclear physics from the University of Tennessee. Prior to joining IBM, Dr. Rao was engaged in research in nuclear physics, digital filters, and digital image processing. He joined IBM to work on large-system scientific and engineering processor design and development. Since 1991 he has been involved in the performance analysis of coupling facility design alternatives and Parallel Sysplex performance.
Gary M. King
IBM System/390 Division, 522 South Road, Poughkeepsie, New York 12601 (garyk@us.ibm.com).
Mr. King is a Senior Technical Staff Member in the S/390 Division, consulting on all aspects of system performance. He joined IBM in 1974 and has been involved in the design and evaluation of system resource managers, most notably in the area of storage management. For the past nine years, his efforts have focused on clustered system performance, particularly the S/390 Parallel Sysplex and its exploiters. He holds five U.S. patents and has received six Outstanding Technical Achievement and Outstanding Innovation Awards in a variety of areas, including storage management, data compression, and performance analysis. Mr. King received a B.S. degree in mathematics from the University at Albany, State University of New York, in 1972 and an M.S. degree in computer science from the Pennsylvania State University in 1974.
Barbara A. Weiler
IBM System/390 Division, 522 South Road, Poughkeepsie, New York 12601 (bajala@us.ibm.com).
Ms. Weiler is an Advisory Software Engineer; she has been working in the S/390 performance area since joining IBM in 1981. Her current responsibilities include performance evaluation of the S/390 Parallel Sysplex, including coupling facility control code (CFCC) and various coupling options. Her previous experience includes processor design analysis and performance evaluation, including Vector Facility performance and FORTRAN performance evaluation. Ms. Weiler received a B.S. degree in mathematics from Marist College in 1974 and an M.S. degree in secondary mathematics education from the State University of New York at New Paltz in 1978.
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