Biographical sketches of authors
Randall J. Easter
IBM System/390 Division, 522 South Road, Poughkeepsie, New York 12601 (reaster@us.ibm.com). Mr. Easter received a B.S. degree in electrical engineering from Pennsylvania State University in 1978, joining IBM that same year. He was involved in the ES/3090 CPU I-element, E-element, and Control Store hardware design. He was the lead engineer on the ES/3090 Vector Coprocessor hardware design team. Later he became team leader and lead engineer for the ES/3090 Integrated Cryptographic Feature (ICRF) Coprocessor. In the early 1990s, he was team leader for the G3/G4 CMOS Cryptographic Coprocessor. Mr. Easter is a Senior Engineer and is currently involved in future cryptographic hardware development. He is an author of twelve filed patents and has received an IBM Division Award, an IBM Outstanding Technical Achievement Award, and, recently, two IBM Outstanding Innovation Awards.
Edward W. Chencinski
IBM System/390 Division, 522 South Road, Poughkeepsie, New York 12601 (chencins@us.ibm.com).
Mr. Chencinski received a B.S. degree in electrical engineering from Lehigh University in 1980, joining IBM that same year. He was involved in the ES/3090 SCE and Expanded Storage hardware design. For the ES/9000, he was involved in the hardware design of the Logic Support Element. In the early 1990s, Mr. Chencinski joined the G3/G4 CMOS Cryptographic Coprocessor hardware design team, focusing on pervasive functions, simulation, and timing. Mr. Chencinski is a Senior Engineer; he is currently involved in future cryptographic hardware development. He is an author of one filed patent and one pending patent and author of several journal articles.
Edward J. D'Avignon
IBM System/390 Division, 522 South Road, Poughkeepsie, New York 12601 (davignon@us.ibm.com).
Mr. D'Avignon received a B.S. degree in computer engineering in 1988 from Syracuse University. He joined IBM that same year and was involved in vector hardware design. In the early 1990s, he joined the G3/G4 CMOS Cryptographic Coprocessor design team, focusing on the PKA engine design. He is an Advisory Engineer currently involved in future cryptographic hardware development. Mr. D'Avignon serves as Vice President of Tau Beta Pi, the engineering honor society. He is an author of one filed patent and three pending patents.
Seth R. Greenspan
IBM System/390 Division, 522 South Road, Poughkeepsie, New York 12601 (sgreensp@us.ibm.com).
Mr. Greenspan received a B.S. degree in electrical engineering in 1988 from the University of Connecticut. Since joining IBM in 1988, he has been involved in the hardware design of the ES/9000 Instruction Execution Element and the Integrated Cryptographic Feature (ICRF). He was a lead designer for the G3/G4/G5/G6 CMOS Cryptographic Coprocessor. Mr. Greenspan is an Advisory Engineer and is currently involved in S/390 cryptographic hardware development. He has received two IBM Outstanding Technical Achievement Awards.
William A. Merz
IBM System/390 Division, 522 South Road, Poughkeepsie, New York 12601 (merz@us.ibm.com).
Mr. Merz received a B.S. degree in electrical engineering in 1981 from the New York Institute of Technology, joining IBM that same year. He was involved in the ES/3090 diagnostic software development and design, and he also contributed to the ES/3090 Integrated Cryptographic Feature (ICRF). In the early 1990s, Mr. Merz was involved with the hardware design for the G3/G4 CMOS Cryptographic Coprocessor RSA engine. He is currently involved in development of microcode for the PCI cryptographic processor. Mr. Merz is an author of one filed patent.
Clark D. Norberg
IBM System/390 Division, 522 South Road, Poughkeepsie, New York 12601 (cnorberg@us.ibm.com).
Mr. Norberg received a B.S. degree in electrical engineering in 1977 from the University of Buffalo. He joined IBM in 1977 and was involved in the IBM 3031 channel and attached processor design. He worked on the ES/3090 IOP hardware design team. Later he became team leader and lead engineer for the ES/9000 Integrated Offload Processor (IOP). In the early 1990s, Mr. Norberg joined the G3/G4 CMOS Cryptographic Coprocessor design team focusing on simulation. He was the design and integration team leader for the G5 CMOS Cryptographic Coprocessor design. Mr. Norberg is a Senior Engineer; he is currently involved in future cryptographic hardware development. He is an author of several journal articles and has received two IBM Outstanding Technical Achievement Awards.
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